:%s/foo/bar/g        Find each occurrence of 'foo' (in all lines), and replace it with 'bar'. 

:s/foo/bar/g         Find each occurrence of 'foo' (in the current line only), and replace it with 'bar'. 

:%s/foo/bar/gc       Change each 'foo' to 'bar', but ask for confirmation first. 

:%s/\<foo\>/bar/gc   Change only whole words exactly matching 'foo' to 'bar'; ask for confirmation. 

:%s/foo/bar/gci      Change each 'foo' (case insensitive) to 'bar'; ask for confirmation. 
                     This may be wanted after using :set noignorecase to make searches case sensitive (the default). 

:%s/foo/bar/gcI      Change each 'foo' (case sensitive) to 'bar'; ask for confirmation. 
                     This may be wanted after using :set ignorecase to make searches case insensitive. 

Search and replace

CR = Carriage Return
LF = Line Feed

sed

NAME          sed - stream editor for filtering and transforming text
DESCRIPTION   Sed is a stream editor. A stream editor is used to perform
              basic text transformations on an input stream.

# DOS => UNIX
# replace every "\r" with ""
$ sed "s/\r//" infile >outfile

# UNIX => DOS
# add in every line-end (RegEx $) before \n the character \r
$ sed "s/$/\r/" infile >outfile

How to convert DOS/Windows newline to Unix newline in bash script?
sed Tutorium – Eine Einführung in sed
Useful one-line scripts for sed

tr

NAME          tr - translate or delete characters
DESCRIPTION   Translate, squeeze, and/or delete characters
              from standard input, writing to standard output.

# delete every "\r"
tr -d \r <infile >outfile

#!/bin/bash

FILES=\
"AAA "\
"BBB "\
"CCC "\
"DDD "\
"EEE "

for FILE in $FILES
do
    echo "# $FILE"
done

# AAA
# BBB
# CCC
# DDD
# EEE

$ find . -exec file {} \;

$ iconv -f UTF-8 -t ISO-8859-15 in.txt > out.txt
$ iconv          -t ISO-8859-15 in.txt > out.txt # ohne input-encoding
$ iconv --from-code UTF-8 --to-code ISO-8859-15 in.txt > out.txt

stackoverflow

Best way to convert text files between character sets?
How to convert ISO8859-15 to UTF8
Linux: Converting a file encoded in ISO-8859-1 to UTF-8

Mit der Column Address Strobe Latency (englisch, kurz CL oder CAS Latency), auch Speicherlatenz genannt, wird die Verzögerung zwischen der Adressierung in einem DRAM-Baustein und der Bereitstellung der an dieser Adresse gespeicherten Daten bezeichnet. Die CL gibt an, wie viele Taktzyklen der Speicherbaustein benötigt, um die während des CAS gelieferten Daten zu verarbeiten, bevor er weitere Befehle entgegennehmen, bzw. das Ergebnis mitteilen kann. Je höher der CL-Wert, desto mehr Taktzyklen werden für die Verarbeitung benötigt, womit auch die davon abhängende Verzögerung größer wird.

Wikipedia

Column Address Strobe Latency
Dymanic Random Access Memory (DRAM) # CAS

Altera VHDL Examples
Die Hardwarebeschreibungssprache VHDL
OpenCores open source hardware IP-cores

RegEx Look-around assertions

Diese Konstrukte erweitern die regulären Ausdrücke um die Möglichkeit, kontextsensitive Bedingungen zu formulieren, ohne den Kontext selbst zu matchen.
Das heißt, möchte man alle Zeichenfolgen „Sport“ matchen, denen die Zeichenfolge „verein“ folgt, ohne dass jedoch die gematchte Zeichenfolge die Zeichenfolge „verein“ selbst enthält, wäre dies mit einer look-ahead assertion möglich: Sport(?=verein)

(?<=(\s|^))entity(?=(\s|$))

(?<=Ausdruck) = positive look-behind assertion
(?=Ausdruck)  = positive look-ahead assertion

Alt (nicht verwenden!):
([^a-z]*|^)entity([^a-z]*|\w|$)
([^a-z ]+|^)entity([^a-z ]+|\w|$)

VHDL

VHDL Design Units and Subprograms
VHDL Coding Style Guidelines

Package

package <PACKAGE_NAME> is
    [...]
end package <PACKAGE_NAME>;

package body <PACKAGE_NAME> is
    [...]
end package body <PACKAGE_NAME>;

“Use” and “Library” in VHDL
Libraries and Packages in VHDL
VHDL: Component vs Entity
VHDL Packages
WORK is not a VHDL Library

Function

function function_name (parameter_list) return type is  
begin
    [...]
end function_name;

function shift_rows (
    X : std_logic;
    Y : std_logic;
    Z : std_logic
) return std_logic is  
begin
    [...]
end shift_rows;

encrypt_block : process(reset_50_n,clock_50_i)
        variable temp_state;

Procedure

procedure <PROCEDURE_NAME> (    
    X : std_logic;
    Y : std_logic;
    Z : std_logic
) is
	declarations
begin
	sequential statements
end procedure_name;

type path_record_i is record
data : std_logic_vector((PATH_DATA_WIDTH_IN_BITS-1) downto 0);
clk : std_logic;
dv : std_logic;
err : std_logic;
end record;

Wikipedia

Data-Warehouse (DWH)
ETL-Prozess (Extract, Transform, Load)
Online Analytical Processing (OLAP)
OLAP-Würfel
Online Transaction Processing (OLTP)

– Analoge Schaltungen
– Digitale Schaltungen
– Simulation (wie TINA oder Proteus)
  o Analog / Digital / Mixed Mode
  o FPGA Devices
    x CPU Interpreter (PIC16, AVR, 8051, HC11, ARM Cortex-M3) mit gcc Integration
  o Oszilloskop / Logik Analyzer / Multimeter
– Peripherals Library
  o Strukturiert / Suchfunktion
  o Symbole selber erstellen mit Makrosprache
  o Analog (Widerstand, Kondensator) / Digital (AND-Gatter, D-FF) / Mixed Übergang (boundry, transitionbzw. Fehlermeldung
  o mit/ohne VCC/GND
  o Bauteile
    x Gleiches Bauteil anders dargestellt: IEC, ANSI, DIN, Graphisch (LED, Taster, Anzeige, Schrittmotoren)
    x Mikrocontroller
    x Ethernet mit Kodierung (Manchesterkodierung, 4B5B-Code) / Modulationsverfahren [Analog, Digital, Puls, Frequenzspreizend] (DSQ, QAM)
    x el. mag. Wellen
    x Schrittmotoren / Treiber
    x Bus-Systeme / Protokolle (SPI, I2C, 1-Wire, RS-232, USB)
    x Taster
    x Anzeige (LED, LCD)
    x FPGA (?)

Proteus VSM Peripherals Library

Standard

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.math_complex.all;

library STD;
use STD.textio;

VHDL standard packages and types

• ‘X’ usually is caused by two statements driving the same signal in opposite directions,i.e., ‘0’ and ‘1’
• ‘Z’ is used to build a tri stated output/input
• ‘L’ and ‘H’ are used to model a pulldown or pullup respectively
• ‘-‘ is used in comparisons when you don’t care about certain bits in a vector

stackoverflow: std_logic in VHDL

Wikipedia

VHDL
Four-valued logic (en)
IEEE 1164 (en)
Dataflow programming (en)

Wikipedia

Espresso heuristic logic minimizer (en)
Logiksynthese
Logic Synthesis (en)
Karnaugh-Veitch-Diagramm
Verfahren nach Quine und McCluskey

Altera

Quartus II Support for SystemVerilog
SystemVerilog with the Quartus II Software (OHDL1125), 1 Hour Online Course