Take control of your VHDL libraries in ModelSim
How to execute ‘Zoom Fit’ in ModelSim/QuestaSim from TCL console?
Simulate with ModelSim (PDF)
$ vsim -c -do sim.do counter -wlf counter.wlf
$ vsim -c -do "onElabError resume; run -all; exit" -f modelsim.tops
$ vsim -do run.do -c -suppress 3829 test
$ vsim -view counter.wlf
Usage: vsim [options] [[<library>.]<primary>[(<secondary>)]]
-c Command line mode
=> instructs ModelSim not to invoke the GUI
-do "<command>" Execute <command> on startup; <command> can be
a macro filename
-wlf <filename> Specify the name of the WLF file (Default: vsim.wlf)
=> saves the simulation results in a WLF file
-f <filename> Read command line arguments from <filename>
-view <filename> View the contents of a WLF file
$ /opt/intelFPGA_lite/18.1/modelsim_ase/bin/vsim -help
Usage: vsim [options] [[<library>.]<primary>[(<secondary>)]]...
-default_radix radix|radix_flag[,radix_flag...] Set default radix and radix flags.
Specifying just a radix will clear all radix flags. Specifying
just radix flags will set the flags but leave the default radix unchanged.
-help Print this message
-version Print the version of the simulator
<library_name>.<design_unit>
Specifies a library and associated design unit; multiple library/design unit
specifications can be made. If no library is specified, the work library is
used.
--------------------------- VHDL and Verilog options ---------------------------
-assertcover Keep assertion counts for coverage statistics
-assertdebug Keep data for debugging assertion failures
-assertfile <filename> Alternative file for recording assert messages
-msgfile <filename> Alternative file for recording non-assert messages
-assume Simulate PSL and Verilog assume directives same as assert directives
-autoexclusionsdisable=fsm|assertions|all|none
Turns on/off automatic fsm or assertions code coverage exclusions
-autoprofile[=<profile_database>]
Automatically collect profile data without requiring the use of profile
commands. Specifying a profile database name is optional
-attemptedimmedcovers Exclude unattempted immediate covers to participate in coverage calculations
-batch Batch mode
-c Command line mode
-capacity[=line] Enable fine grain capacity analysis.
Optional line option enables line based capacity reporting.
-colormap new Specifies that the window should have a new private colormap instead of
using the default colormap for the screen.
-coverage Allows enabled coverage statistics to be kept
-coverenhanced Enables functionality which may change the appearance or content of coverage
metrics. A detailed list of these changes can be found by searching in the
release notes for 'coverenhanced'. This option only takes meaningful effect in
letter releases (e.g. 10.2b). It has no effect in initial major releases (e.g. 10.2).
-covercountnone Disables the default behavior to increment the count of all matching rows in
condition and expression coverage UDP tables. Has no effect on FEC coverage.
-coverstore <path> Specifies the path where coverage data will be dumped during exit
of a simulation run. The -testname argument is required for this
option to specify a testname for the current simulation run.
-do "<command>" Execute <command> on startup; <command> can be
a macro filename
-display <display-spec> Specifies the name of the display to use.
Does not apply to Windows platforms.
-displaymsgmode <mode> Controls transcripting of display system task messages.
Messages will appear in transcript and/or MsgViewer (.wlf file)
Valid modes - tran, wlf, both (Default: tran)
+delayed_timing_checks Causes timing checks to be performed on the delayed versions of input ports
+dumpports+direction Provide port direction info in VCD file for dumpports
+dumpports+unique Provide unique Extended VCD identifier for each port
+dumpports+no_strength_range
Ignore strength range when resolving conflicts
+dumpports+collapse Collapse dumpport vectors into single VCD ids
+dumpports+nocollapse Don't collapse dumpport vectors into single VCD ids
+dumpports+force_direction
Ignore driver location. Use port direction for input and output ports
-f <filename> Read command line arguments from <filename>
-optionset <optionset_name>
Calls an option set in modelsim.ini.
-g<Name>=<Value> Specify generic/parameter default Value for Name
-g <Name>=<Value> Alternate way to specify generic/parameter default Value for Name
-G<Name>=<Value> Override generic/parameter with specified Value
-G <Name>=<Value> Alternate way to override generic/parameter with specified Value
-geometry <geometry_spec> Specifies the size and location of the main window.
Where <geometry_spec> is of the form: WxH+X+Y
-gblso <shared_obj>[,<shared_obj>...] Open the specified shared object(s) with global
symbol visibility. If multiple shared objects are specified,
they will first be merged internally and then loaded as single shared object.
-gui Open the GUI without loading a design
-i Force interactive mode
-ignoreinilibs Ignore the libraries specified with the 'LibrarySearchPath' variable in the vsim
section of the ini file
-immedassert Enable SystemVerilog and VHDL immediate assertions
-installcolormap Cause the application to use its own color map
-keeploaded Prevent the simulator from unloading/reloading
shared libraries
-keeploadedrestart Prevent the simulator from unloading/reloading
shared libraries during restart
-keepstdout Do not redirect stdout to transcript window
-l <filename> Write simulation log to <filename>
(Default: transcript)
-learn <fname> Learn the names of objects externally accessed at runtime
(by methods such as PLI, VPI, Signal Spy, or CLI).
<fname>.ocf, <fname>.ocm and <fname>.acc files created
-lib <libname> Load top-level design units from <libname>
(Default: work)
-work <libname> Work library to write the optimized design into.
(Default: top-level library i.e. <libname> used with -lib option)
-lic_noqueue Do not wait in the license queue when a license
is not available
-lic_vhdl Immediately reserve a VHDL license
-lic_vlog Immediately reserve a Verilog license
-lic_no_viewer Disable checkout of viewer license and always use a
simulation license to view
-lic_viewsim View with a simulation license if a viewer license
is not available
-logfile <filename> Write simulation log to <filename>
(Default: transcript)
-memprof Collect memory allocation profile data for use with
current simulation
-memprof+call Unwinds the call stack and collects the call tree information.
-memprof[+file=<filename>]
Collect memory allocation profile data for use with
current simulation and copy raw data to <filename>
-memprof[+fileonly=<filename>]
Collect memory allocation profile data in raw format
to <filename>
-modelsimini <modelsim.ini>
Specify path to the modelsim.ini file
-mlopt Optimize mixed language nets
-multisource_delay min|max|latest
Controls annotation of SDF INTERCONNECT construct
(Default: max)
+multisource_int_delays Enable multisource interconnect delays
for both Verilog and VHDL
-msglimit [all,|none,][-|+]<msgNumber>[,[-|+]<msgNumber>...]
Limit the listed messages to display five times
-msglimitcount <limit_value> -msglimit [all,|none,][-|+]<msgNumber>[,[-|+]<msgNumber>...]
Limit the reporting of listed messages to user defined count
-msgsingleline Display the messages in a single line.
-msgmode <mode> Controls transcripting of elaboration/runtime messages.
Messages will appear in transcript and/or MsgViewer (.wlf file)
Valid modes - tran, wlf, both (Default: tran)
-multicount <covtypes> Specifies the single-bit or multi-bit count modes for bins of
different coverage types
-mvchome <path> Location of Questa Verification IP installation.
Overrides 'MvcHome' modelsim.ini setting
-name <name> Specifies the application name used by the interpreter for send commands.
+no_notifier Disable notifier toggling for timing constraint
violations
-noappendclose Do not physically close VHDL files when they are opened in append mode.
-noassertcover Do not keep assertion counts for coverage statistics
-noassertdebug Do not keep data for debugging assertion failures
-noassume Do not simulate PSL and Verilog assume directives
-nocapacity Do not display capacity related information
-noexcludehiz Do not automatically exclude rows with Hi-Z for
expression coverage
-noexcludeternary Disables the automatic exclusion of UCDB coverage data rows resulting
from ternary expressions for the entire design.
-nolog Do not generate a simulation log file
-nopsl Disable PSL assertions
-nostdout Do not write transcript to stdout (batch mode only)
+no_tchk_msg Disable timing constraint error messages
-note <msgNumber>[,<msgNumber>...] Change the severity of the listed
messages to Note
+notimingchecks Disable Verilog and VITAL timing checks
-novhdlvariablelogging Disables higher performance VHDL variable logging
-nosyncio Disables synchronization of I/O from different
sources like C/C++ application(PLI,VPI,DPI)
and GUI. vsim will perform better when it does
not have to synchronize I/Os. This option is on
by default with -batch
-nowiremodelforce Restores the force command to previous usage (prior to version 10.0b)
where an input port cannot be forced directly if it is mapped at a
higher level in VHDL and mixed models. Signals must be forced at the
top of the hierarchy connected to the input port.
-onfinish <mode> Customize the kernel shutdown behavior at the end of simulation
Valid modes - ask, stop, exit, final (Default: ask)
-pa Enable PowerAware RTL mode
-pa_allowtimezeroevent[=all]
Enable corruption, isolation, or release of signals at time 0 for
the following events: pa_corrupt_register, pa_iso_on and pa_iso_off.
-pa_debugdir <directory> Specify the location for the writing and retrieval of post-simulation
debug information for power aware simulations.
-pa_disabletimezeroevent Disable the default behavior of the -pa_allowtimezeroevent switch.
-pa_gls <testbench_top> Enables gate-level simulation for Power Aware, performed on the
top-of-design test bench (testbench_top).
-pa_highlight Enables visual indication (highlighting) of power states of signals viewed
in the Wave window.
-pa_loadimdb Load the information model database in vsim.
-pa_lib <libname> Use PA specific dumps from <libname> library. (Default: work)
-pa_db <filename> Use QPADB specific dumps from <filename>. (Default: Current Working Directory)
-pa_togglelimit=<n> Instructs vsim to discontinue reporting an error (8906) for each signal
that toggles during power off and issue note (8922) instead.
The default value is 5.
-pa_top <dut path> Allow vsim to use different top level hierarchy for PA
(Example: -pa_top /tb2/dut_inst
-pa_zcorrupt Change the default corruption value used at power-down from 'X' to 'Z'.
-debugdb[=<dbname>] To create or use Schematic Debug database (Default: vsim.dbg)
-postsimdataflow Needed with -debugdb, to enable post simulation dataflow
-pedanticerrors Enforce strict language checks
-permissive Relax some language error checks to warnings.
-printsimstats[=[val][v]] Print simstats results
Possible values: 0 - disable simstats, 1 - end of simulation(default)
2 - end of each run command and simulation, v - verbose stats
-psl Enable PSL assertions
-psloneattempt Force single PSL assertion coverage attempt
-pslinfinitythreshold Redefine infinite clock tick for strong operators
-quiet Do not report 'Loading...' messages
-qwavedb=<options>... Use qwavedb to log event data in place of wlf
-runinit Execute run -init before command prompt or running -do files.
-sdfmax[@<delayScale>] [<instance>=]<sdffile>
Annotate VITAL or Verilog <instance> with maximum
timing from <sdffile>, scaled by <delayScale>
-sdfmaxerrors <n> Max number of missing instances reported (default is 5)
-sdfmin[@<delayScale>] [<instance>=]<sdffile>
Annotate VITAL or Verilog <instance> with minimum
timing from <sdffile>, scaled by <delayScale>
-sdfminr[@<delayScale>] [<instance>=]<sdffile>
Specifies when an instance of a Preoptimized Design Unit
(vopt -pdu) with an associated default SDF
file is to be re-annotated with minimum, typical, or
maximum timing from the specified SDF file.
-sdfnoerror Treat SDF errors as warnings
-sdfnowarn Disable warnings from SDF annotator
-sdfreport=<fileName> Report unannotated/partially-annotated specify objects into <fileName>
+sdf_report_unannotated_insts Enable error messages for any un-annotated Verilog instances with
specify blocks or VHDL instances with VITAL timing generics that are under
regions of SDF annotation.
-sdftyp[@<delayScale>] [<instance>=]<sdffile>
Annotate VITAL or Verilog <instance> with typical
timing from <sdffile>, scaled by <delayScale>
+sdf_verbose Display SDF annotator status messages
-showautoexcludprows Display auto-excluded UDP rows of table, in expression coverage
-showlibsearchpath Show all the libraries which will be searched for precompiled modules
-suppress <msgNumber>[,<msgNumber>...] Suppress the listed messages
-stats[=[+-]<args>] Enables simulation statistics
<args> are all,none,time,cmd,msg,perf,verbose,list,kb,eor
-sync Executes all X server commands synchronously, so that errors are reported
immediately. Does not apply to Windows platforms.
-syncio Enable I/O synchronization with -batch option
where I/O synchronization is disabled by default
for optimal performance.
-undefsyms=[<args>] Generate stubs for undefined symbols in the shared libraries being loaded
<args> are on, off, verbose
-t [1|10|100]fs|ps|ns|us|ms|sec Time resolution limit
(VHDL default: resolution setting from .ini file)
(Verilog default: minimum time_precision in the
design)
-tag <string> Set tag for FLI/PLI tracing to <string>
-notoggleints Excludes VHDL integers from toggle coverage
-testname <name> Specifies a testname for the current simulation run. Required
only when coverage data is saved in a coverstore.
-togglemaxintvalues Sets max number of values saved for VHDL integers
-togglemaxrealvalues Sets max number of values saved for SystemVerilog reals
-togglemaxfixedsizearray <size>
Sets the limit on the size of Verilog unpacked fixed-size arrays
that are included for toggle coverage
-togglecountlimit Sets max count saved for a toggle node
-togglewidthlimit Sets max width for vectors counted for toggles
-togglevlogreal Includes Verilog real type in toggle coverage
-togglefixedsizearray Includes Verilog unpacked fixed-size arrays, VHDL multi-d arrays and VHDL arrays-of-arrays in toggle coverage
-togglevlogints Includes Verilog integers for toggle coverage
-togglevhdlrecords Includes VHDL records for toggle coverage
-notogglevlogints Excludes Verilog integers from toggle coverage
-notogglevlogreal Excludes Verilog real type in toggle coverage
-notogglefixedsizearray Excludes Verilog unpacked fixed-size arrays, VHDL multi-d arrays and VHDL arrays-of-arrays in toggle coverage
-notogglevhdlrecords Excludes VHDL records from toggle coverage
-nowlfdeleteonquit Preserve the current simulation WLF file (vsim.wlf) when the simulator exits.
-togglepackedasvec Treat SystemVerilog packed structures and multi-d arrays as flattened vectors
-togglevlogenumbits Treat SystemVerilog enums as reg-vectors for toggle coverage
-extendedtogglemode [1|2|3]
Change the level of support for extended toggles.
The levels of support are:
1 - 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z')
2 - 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'
3 - 0L->1H & 1H->0L & all 'Z' transitions
-toggleportsonly Enable toggle statistics collection only for ports
-toggledeglitch <period> Enable toggle deglitching. Require signal stable longer than period value
<period> must be a time value with units
-title <string> Optional title for the Main window
-trace_dpi <n> Set DPI tracing to level <n>. The default is 0 which turns off tracing.
The levels of support are:
1 - turning on all tracing
0 - turning off all tracing (default)
i - turning on the tracing of DPI import call only
e - turning on the tracing of DPI export call only
a - turning on the tracing of DPI import/export call arguments only
-trace_foreign <n> Set FLI/PLI tracing to level <n>
-ucdbteststatusmsgfilter <TCL style regular expression>
Matching messages do not propagate their status to UCDB TESTSTATUS
-unattemptedimmed Include immediate assertions to participate in assertion coverage calculations
-valgrind "[options]" same as SystemC -valgrind option
-vcdstim [<instance>=]<filename> Stimulate the top-level design or instances
from an Extended VCD file
-vhdlmergepdupackage VHDL packages with the same name and same library are shared between PDUs
-vhdlseparatepdupackage VHDL packages with the same name and same library are not shared between PDUs
-vhdlvariablelogging Enables higher performance VHDL variable logging
-visual <visual> Specify the visual to use for the window. Does not apply to Windows platforms.
-visualizer[=<bin-file><visualizer-options>...] Visualizer interactive mode
-view [<dataset>=]<filename> View the contents of a WLF file
-viewcov [<dataset>=]<ucdbfilename> View the contents of the coverage ucdb file
-warning <msgNumber>[,<msgNumber>...] Change the severity of the listed
messages to Warning
-warning error Report all warnings as errors
-wlf <filename> Specify the name of the WLF file (Default: vsim.wlf)
-wlfcompress Create compressed WLF files.
-wlflock Lock a WLF file.
-wlfopt Turn on WLF file optimizations (default)
-nowlfopt Turn off WLF file optimizations
-nowlfcompress Turn off WLF file compression
-nowlflock Turn off WLF file locking
-wlfslim <size> Specify maximum number of Megabytes to be saved in
WLF file (Default: infinite)
-wlftlim <duration> Specify maximum duration of time to be saved in
WLF file (Default: all)
-wlfcachesize <n> Specify WLF reader cache size (per WLF file.)
(Default: no reader cache)
-wlfsimcachesize <n> Specify WLF reader cache size for current simulation
(Default: no reader cache)
-wlfdeleteonquit Delete WLF file when simulation quits.
-nowlfcollapse Log every item event and preserve event order.
-wlfcollapsedelta Log item values only at end of iteration. (default)
-wlfcollapsetime Log item values only at end of time step.
--------------------------------- VHDL options ---------------------------------
-absentisempty Treat non-existent VHDL files opened for read
as empty
-accessobjdebug Enable access value designated object debug features.
-defaultstdlogicinittoz Sets the default VHDL initialization of std_logic to "Z" (high impedance)
for ports of type OUT and INOUT.
-nocollapse Disable optimization of internal port map connections
-nofileshare Do not share file descriptors for VHDL files opened
for write or append that have identical names
-noglitch Disable VITAL glitch generation
+no_glitch_msg Disable glitch error messages
-oldvhdlforgennames Enable the use of a previous style of naming in VHDL for...generate
statement iteration names in the design hierarchy.
-stackcheck Enable runtime stack usage sanity checking.
-std_input <filename> Use filename for VHDL textio STD_INPUT file
-std_output <filename> Use filename for VHDL textio STD_OUTPUT file
-strictvital Sacrifice performance for strict VITAL compliance
-vital2.2b Select SDF mapping for VITAL 2.2b (Default: VITAL 95)
-vital_fix_negative_setup_hold_sum
Set negative time to zero when setuphold sum is negative
-------------------------------- Verilog options -------------------------------
-allowcheckpointcpp 1|0 Turn on/off the support for checkpointing foreign C++ libraries.
Must be used in the vsim session where a checkpoint is created.
+alt_path_delays Use current output value instead of pending value
when selecting inertial specify path output delay
+bitblast[=[iopath|tcheck]] Bit-blast Verilog specify paths and/or tchecks with wide ports.
Without the optional qualifiers operates on specify paths and tchecks.
+bitblast=iopath bit-blasts specify paths with wide ports.
+bitblast=tcheck bit-blasts tchecks with wide ports.
-checkvifacedrivers 1|0 Include assignments through virtual interfaces in the multiple-driver analysis.
-classdebug Enable class debug features.
-nocvgcollapseembeddedinstances
Turning off the optimization of collapsing embedded covergroup
instances when type_option.merge_instances is set to zero.
-cvgmaxrptrhscross Set the maximum cross bin BINRHS terms in coverage report.
-cvgprecollect <ucdb_filename>
Specify a UCDB file as optimization control for the current
simulation. This switch can occur multiple times.
-cvgprecollectlog <log_filename>
Specify the path of the log file where the precollect processing information
will be written to.
-cvgperinstance Force the option.per_instance control in all covergroup declarations to 1.
-cvgsingledefaultbin Collapse a Covergroup default array bin into a scalar bin
-cvghaltillbin Halt simulation when an illegal cover/cross bin gets hit
-cvgmergeinstances Set the default value of covergroup type_option.merge_instances to 1
-cvgsparsecross Force modelling of Covergroup cross bins in a sparse fashion.
-cvgsparsearraybin Force modelling of Covergroup unsize array bins in a sparse fashion.
-cvgzwnocollect <1|0> Turn on/off the coverage data collection of zero-weight coverage items.
-cvgbintstamp Record simulation timestamp when a covergroup bin is covered during simulation run
-cvgopt[=[+|-]<mode>[,[+|-]<mode>]*]
Enable Covergroup optimization modes.
Valid modes are:
minhitcnt - stop sampling coverpoint/cross when it is fully covered.
-nocrossautobins[=[uncond|cond]] Avoid generating auto bins in cross coverage computation.
-noimplicitcoverpoint Avoid collecting coverage for implicit coverpoints.
+autofindloop Find the infinite zero-delay loop when Iteration Limit is exceeded.
This option should be used with full design visibility e.g. vopt +acc
-hazards Enable hazard checking
+initmem+<seed> Specify seed value to be used for randomizing
fixed-size arrays marked for randomization by vlog/vopt.
+initreg+<seed> Specify seed value to be used for randomizing
variables marked for randomization by vlog/vopt.
-initreport <filename> Report initial values generated due to
applying +initreg/+initmem options to vlog/vopt
+initregNBA | +noinitregNBA
Controls whether +initreg settings applied to registers
of sequential UDPs should be non-blocking. This is useful when continuous
assignments overwrite register initialization.
+initregNBA -- (default) enables this functionality
+noinitregNBA -- disables this functionality.
+int_delays Optimize annotation of interconnect delays
-L <libname> Search library for design units instantiated from
Verilog and for VHDL default component binding
-Lf <libname> Same as -L, but libraries are searched before `uselib
-Ldir <dirname> Specify the container folder for libraries passed with -L and -Lf options.
-libverbose[=prlib] Verbose messaging about library mappings, search and resolution.
The =prlib modifier prints out the -L/-Lf/-Ltop option that was used
to locate each design unit loaded by vsim.
-noltop Stops promotion of libraries containing top design units to searchable libraries.
+maxdelays Use maximum timing from min:typ:max expressions
+mindelays Use minimum timing from min:typ:max expressions
+no_autodtc Turn off auto-detection of optimized cells with negative timing checks
and autoapplication of +delayed_timing_checks to those cells.
+no_cancelled_e_msg Disable negative pulse warning messages
-noimmedca Revert to pre-6.5 continuous assignment event ordering
+no_neg_tchk Set negative timing check limits to zero
+no_path_edge Ignore the input edge specification on path delays
+no_pulse_msg Disable path pulse error warning messages
+nosdferror Treat SDF errors as warnings
+nosdfwarn Disable warnings from SDF annotator
+no_show_cancelled_e Cancel negative pulse (Default)
+nospecify Disable specify path delays and timing checks
+notiftoggle01[+<seed>] Use the metastable UDP evaluation of enabled Verilog cells in simulation.
Default seed value is 0
-no_autoacc Prevents vsim from automatically passing the +acc switch to vopt.
-nosva Disable SystemVerilog concurrent assertions
-noimmedassert Disable SystemVerilog and VHDL immediate assertions
-nocvg Disable Covergroup object construction and builtin calls
-nocvgmergeinstances Set the default value of covergroup type_option.merge_instances to 0
-nocvgperinstance Force the option.per_instance control in all covergroup declarations to 0.
-nocvgzwopt Enable sampling for zero weight covergroup items
-no_risefall_delaynets Disables the rise/fall delay net delay negative timing check algorithm.
+nowarnBSOB Disables run-time warning messages for bit-selects in initial blocks
that are out of bounds
+nowarn<CODE | Number> Disable specified warning message
(Example: +nowarnTFMPC)
+ntc_warn Enable warnings from negative timing constraint
algorithm
+ntcnotchks Disable timing checks while maintaining NTC delays
-pli "<object list>" Load the list of PLI shared objects
-plicompatdefault [latest | 2009 | 2005 | 2001]
Specify the VPI object model behavior within vsim. This switch applies
globally, not to individual libraries.
+<plusarg> Option accessible by PLI routine mc_scan_plusargs
+pulse_e/<percent> Set path pulse error limit as percentage of
path delay
+pulse_e_style_ondetect Drive pulse error state immediately on detection
+pulse_e_style_onevent Drive pulse error state on time of pending event
(Default)
+pulse_int_e/<percent> Set interconnect pulse error limit as percentage
of delay
+pulse_int_r/<percent> Set interconnect pulse rejection limit as
percentage of delay
+pulse_r/<percent> Set path pulse rejection limit as percentage of
path delay
+sdf_iopath_to_prim_ok Prevent vsim from issuing an error when it cannot locate specify path
delays to annotate
+sdf_nocheck_celltype Disable check between SDF celltype name and
module name
+show_cancelled_e Drive pulse error state on negative pulse
-solvefailseverity=<value>
Specify error message severity when randomize() failure is detected
Valid values:
0 - no error
1 - warning
2 - error
3 - failure
4 - fatal
-solvebeforeerrorseverity=<value>
Specify error message severity for suppressible errors that
are detected in a solve/before constraint
Valid values:
0 - no error
1 - warning
2 - error
3 - failure
4 - fatal
-solveengineerrorseverity=<value>
Specify error message severity for suppressible errors that
are related to solve engine capacity limits
Valid values:
0 - no error
1 - warning
2 - error
3 - failure
4 - fatal
-solveengine <engine> Use specified solver engine to evaluate randomize() scenarios
Valid engines - auto, bdd, act
-solvefaildebug[=value] Display constraint conflicts on randomize() failure
Valid values:
0 - disable solvefaildebug
1 - basic debug (no performance penalty)
2 - enhanced debug (runtime performance penalty)
If no value is specified, basic debug will be enabled.
-solvefailtestcase[=filename]
Upon encountering a randomize() failure, generate a
simplified testcase that will reproduce the failure.
Optionally output the testcase to the specified file.
Testcases for 'no-solution' failures will only be
produced if -solvefaildebug is enabled.
-solveprofile Enable randomize() profiling (profile data included in solver report)
-solverev <version> Specify random sequence compatibility with <version>
(Example: -solverev 6.2a)
-solvetimeout <value> Specify solver timeout threshold (in seconds). randomize() will fail
if the CPU time required to evaluate any randset exceeds the specified
timeout. A value of 0 will disable timeout failures.
-solveverbose Print information about randomize() call processing
-sv_seed <seed|random> Specify seed value (or 'random') for the random number
generator (RNG) of the SystemVerilog root thread
-sv_reseed <seed|random> Reseed existing SystemVerilog RNGs with specified seed
value (or 'random') when restoring from checkpoint
-sva Enable SystemVerilog concurrent assertions
-svext=[+|-]<extension>[,[+|-]<extension>]*
Enable/disable non-LRM compliant SystemVerilog language extensions
Valid extensions are:
cfce - generate an error if $cast fails as a function
dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks
expdfmt - enable format string extensions for $display/$sformatf
extscan - Support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi)
fmtcap - prints capital hex digits with %X/%H in display calls
iddp - ignore DPI disable protocol check
noexptc - ignore DPI export SV type name overloading check
lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h")
realrand - support randomize() with real variables and constraints (Default)
-svrandext=[+|-]<extension>[,[+|-]<extension>]*
Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions
Valid extensions are:
forkjoinstab - preserve parent thread random stability when seeding fork/join sub-threads (Default)
nonrandstab - disable seeding of "non-random" class instances (Default)
nodist - interpret 'dist' constraint as 'inside' (ACT only)
noorder - ignore solve/before ordering constraints (ACT only)
packrandidx - allow random index for packed variable in constraint (Default)
promotedist - promote priority of 'dist' constraint if LHS has no solve/before
skew - skew randomize results (ACT only)
-tab <filename> Specify PLI TAB file
-tbxhvllint Enables TBX to identify delays encountered at runtime, with file name
line number and the delay maturity time. (This feature depends on
libraries that have been compiled with -tbxhvllint specified to vlog)
+transport_int_delays Use transport mode for interconnect delays
+transport_path_delays Use transport mode for path delays
(Default: inertial)
+typdelays Use typical timing from min:typ:max expressions
(Default)
-udpcountlimit [<n> | 0 ] Limit the number of counts that are tracked for UDP Coverage.
-usenonstdcoveragesavesysf Replaces implementation of the built-in, IEEE 1800 compliant
system function with the non-standard variant, and thus affects all
calls to $coverage_save().
-uvmcontrol=[all,disable,struct,reseed,msglog,trlog,certe]
Control specific UVM-aware debug options
+vlog_retain_on | +vlog_retain_off
Enable or disable SDF RETAIN delay processing.
+vlog_retain_on is the default behavior.
+vlog_retain_same2same_on | +vlog_retain_same2same_off
Enable or disable SDF RETAIN delay processing of X insertion on outputs
that do not change, but the causal inputs change.
+vlog_retain_same2same_on is the default behavior.
-v2k_int_delays Use Verilog 2000 style interconnect delays
-vpicompatcb Enable legacy VPI callback ordering prior to 10.5.
-wreal_resolution <resolver>[,check|,nocheck ]
Specify resolve behavior for AMS wreal net
with multiple drivers, where <resolver> is
default, 4state, sum, avg, min, or max.
check/nocheck determine if compatibility with
nettype real resolution functions is to be checked.
-wrealdefaultzero Sets the default value for an undriven wreal net to zero (0).
-gconrun/-nogconrun Enable/disable garbage collection after each simulation run command.
-gconstep/-nogconstep Enable/disable garbage collection after each step command.
-gcthreshold <n> Specify the threshold for Garbage Collection.
The default size is 100. (i.e. Garbage Collection will be
triggered after every 100M byte of class object allocation.)
-------------------------------- SystemC options -------------------------------
-cpppath </path/to/[gcc|g++]>
Specify path to the desired GNU compiler.
Use same compiler path as specified on the sccom
command line.
-cppinstall <[gcc|g++] version>
Specify the version of the desired GNU compiler
supported and distributed by Mentor.
Use same compiler path as specified on the sccom command line.
-enabledpisoscb Enable calling DPI export task/function from the SystemC start_of_simulation callback
-noautoldlibpath Disable setting of LD_LIBRARY_PATH set internally.
-sc22 Use the IEEE 1666-2005 standard (default: IEEE 1666-2011).
-sc_arg <arg> Specify a SystemC command line argument
accessible using sc_main(), sc_argc() and
sc_argv()
-scdpidebug Turn on debugging for SystemC DPI export function call
-sclib <libname> Load the SystemC shared library from <libname>
By default the systemc.so shared library is loaded
from the library in which the top level SystemC design
unit is compiled. This option should be used when systemc.so
is not in the same library as the top level SystemC design unit.
-scstacksize <value> Set SystemC thread stack size. The stack size is set as an integer
number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
Gb(Giga-byte). Examples: '1000 Kb', '1 Mb', '1 Gb'
-noscmainscopename Strip sc_main() scope from the hierarchical path.
-valgrind "[options]" Run valgrind in simulation with user given options
------------------------------ Visualizer options ------------------------------
-qwavedb[=+<option>[+<option>+...]]
Specifies the name of the qwave.db simulation database file and
other logging-related option settings. Options are:
[+rollover[=<file-size>[,<num-files>]]] Rollover files.
[+assertion[=pass]] Log assertions.
[+class[=<filter_file.txt>]] Log classes.
[+displaymsgmode[=log | both | tran]] Log $display, etc messages.
[+glitch] Retain glitches in waveform data.
[+dynarray[=<max-depth>]] Log dynamic arrays.
[+maxbits[=<n>]] Adjust max. size of a (packed) wave.
[+memory[=<max-depth>[,<max-dim>]]] Log memories.
[+msgmode[=log | both | tran]] Log simulation messages
[+queue] Log queues
[+report[=class]] Report everything logged.
[+signal[=<signals>.txt]] Log items listed in a file.
[+statictaskfunc] Log parameters and static variables in SV tasks and functions.
[+transaction[=uvm | vip | transaction_filter_file.txt]]
Log transactions.
[+vhdlvariable] Log VHDL variables.
[+wavefile[=<filename>.db]] Set the name of the qwave.db file.
-visualizer[=<file.bin>] Used during simulation to provide the name of required design.bin file
containing design information for the GUI.
