| Type 1 Tag | Broadcom Topaz | ||
| Type 2 Tag | NXP Mifare Ultralight, NXP Mifare Ultralight C, NXP NTAG | ||
| Type 3 Tag | Sony FeliCa | ||
| Type 4 Tag | NXP DESFire, NXP SmartMX-JCOP |
RFID Selection Guide (PDF)
RFID vs. NFC: What’s the Difference?
NFC Chiptypen
nRF52 as NFC reader
Mifare
nRF52 NFC operation modes
nRF52 -PN532 – reading Mifare Classic
nRF52 write NFC Tag
| AAR | Accelerated address resolver |
| ACL | Access control lists |
| CCM | AES CCM mode encryption |
| COMP | Comparator |
| CRYPTOCELL | ARM TrustZone CryptoCell 310 |
| ECB | AES electronic codebook mode encryption |
| EGU | Event generator unit |
| GPIO | General purpose input/output |
| GPIOTE | GPIO tasks and events |
| I2S | Inter-IC sound interface |
| LPCOMP | Low power comparator |
| MWU | Memory watch unit |
| NFCT | Near field communication tag |
| PDM | Pulse density modulation interface |
| PPI | Programmable peripheral interconnect |
| PWM | Pulse width modulation |
| QDEC | Quadrature decoder |
| QSPI | Quad serial peripheral interface |
| RADIO | 2.4 GHz radio |
| RNG | Random number generator |
| RTC | Real-time counter |
| SAADC | Successive approximation analog-to-digital converter |
| SPI | Serial peripheral interface master |
| SPIM | Serial peripheral interface master with EasyDMA |
| SPIS | Serial peripheral interface slave with EasyDMA |
| SWI | Software interrupts |
| TEMP | Temperature sensor |
| TWI | I2C compatible two-wire interface |
| TIMER | Timer/counter |
| TWIM | I2C compatible two-wire interface master with EasyDMA |
| TWIS | I2C compatible two-wire interface slave with EasyDMA |
| UART | Universal asynchronous receiver/transmitter |
| UARTE | Universal asynchronous receiver/transmitter with EasyDMA |
| USBD | Universal serial bus device |
| WDT | Watchdog timer |
Part of HAL (lowest layer!) #define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) #define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) #define NRF_BPROT ((NRF_BPROT_Type*) NRF_BPROT_BASE) #define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) #define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) #define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) #define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) #define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) #define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) #define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) #define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) #define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) #define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) #define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) #define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) #define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) #define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) #define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) #define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) #define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) #define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) #define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) #define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) #define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) #define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) #define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) #define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) #define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) #define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) #define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) #define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) #define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) #define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) #define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) #define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) #define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) #define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) #define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) #define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) #define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) #define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) #define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) #define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) #define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) #define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) #define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) #define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) #define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) #define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) #define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) #define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) #define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) #define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) #define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) #define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) #define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) #define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) #define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) #define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) #define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) #define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) #define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) #define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) #define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) #define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE)
| Header File | Processor |
|---|---|
| core_cm0.h | for the Cortex-M0 processor |
| core_cm0plus.h | for the Cortex-M0+ processor |
| core_cm3.h | for the Cortex-M3 processor |
| core_cm4.h | for the Cortex-M4 processor |
| core_cm7.h | for the Cortex-M7 processor |
| core_cm23.h | for the Cortex-M23 processor |
| core_cm33.h | for the Cortex-M33 processor |
| core_sc000.h | for the SecurCore SC000 processor |
| core_sc300.h | for the SecurCore SC300 processor |
| core_armv8mbl.h | for the Armv8-M Baseline processor |
| core_armv8mml.h | for the Armv8-M Mainline processor |
APSR_Type IPSR_Type xPSR_Type CONTROL_Type NVIC_Type SCB_Type SCnSCB_Type SysTick_Type ITM_Type DWT_Type TPI_Type MPU_Type FPU_Type CoreDebug_Type
typedef enum {
/* === ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on */
/* Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, */
/* cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, */
/* including Access Violation */
/* and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, */
/* Memory Access Fault, */
/* other address/memory */
/* related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. */
/* Undef Instruction, */
/* Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via */
/* SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for SV */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* === nrf52 Specific Interrupt Numbers ================================================ */
POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
RADIO_IRQn = 1, /*!< 1 RADIO */
UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
NFCT_IRQn = 5, /*!< 5 NFCT */
GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
SAADC_IRQn = 7, /*!< 7 SAADC */
TIMER0_IRQn = 8, /*!< 8 TIMER0 */
TIMER1_IRQn = 9, /*!< 9 TIMER1 */
TIMER2_IRQn = 10, /*!< 10 TIMER2 */
RTC0_IRQn = 11, /*!< 11 RTC0 */
TEMP_IRQn = 12, /*!< 12 TEMP */
RNG_IRQn = 13, /*!< 13 RNG */
ECB_IRQn = 14, /*!< 14 ECB */
CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
WDT_IRQn = 16, /*!< 16 WDT */
RTC1_IRQn = 17, /*!< 17 RTC1 */
QDEC_IRQn = 18, /*!< 18 QDEC */
COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
TIMER3_IRQn = 26, /*!< 26 TIMER3 */
TIMER4_IRQn = 27, /*!< 27 TIMER4 */
PWM0_IRQn = 28, /*!< 28 PWM0 */
PDM_IRQn = 29, /*!< 29 PDM */
MWU_IRQn = 32, /*!< 32 MWU */
PWM1_IRQn = 33, /*!< 33 PWM1 */
PWM2_IRQn = 34, /*!< 34 PWM2 */
SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
RTC2_IRQn = 36, /*!< 36 RTC2 */
I2S_IRQn = 37, /*!< 37 I2S */
FPU_IRQn = 38 /*!< 38 FPU */
} IRQn_Type;
/* Memory mapping of Cortex-M4 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
uint32_t NVIC_GetPriorityGrouping(void)
void NVIC_EnableIRQ(IRQn_Type IRQn)
void NVIC_DisableIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetActive(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
void NVIC_SystemReset(void)
uint32_t SysTick_Config(uint32_t ticks)
uint32_t ITM_SendChar (uint32_t ch)
int32_t ITM_ReceiveChar (void)
int32_t ITM_CheckChar (void)
void __enable_irq(void) void __disable_irq(void) uint32_t __get_CONTROL(void) void __set_CONTROL(uint32_t control) uint32_t __get_IPSR(void) uint32_t __get_APSR(void) uint32_t __get_xPSR(void) uint32_t __get_PSP(void) void __set_PSP(uint32_t topOfProcStack) uint32_t __get_MSP(void) void __set_MSP(uint32_t topOfMainStack) uint32_t __get_PRIMASK(void) void __set_PRIMASK(uint32_t priMask) void __enable_fault_irq(void) void __disable_fault_irq(void) uint32_t __get_BASEPRI(void) void __set_BASEPRI(uint32_t value) void __set_BASEPRI_MAX(uint32_t value) uint32_t __get_FAULTMASK(void) void __set_FAULTMASK(uint32_t faultMask) uint32_t __get_FPSCR(void) void __set_FPSCR(uint32_t fpscr) void __NOP(void) void __WFI(void) void __WFE(void) void __SEV(void) void __ISB(void) void __DSB(void) void __DMB(void) uint32_t __REV(uint32_t value) uint32_t __REV16(uint32_t value) int32_t __REVSH(int32_t value) uint32_t __ROR(uint32_t op1, uint32_t op2) uint32_t __RBIT(uint32_t value) uint8_t __LDREXB(volatile uint8_t *addr) uint16_t __LDREXH(volatile uint16_t *addr) uint32_t __LDREXW(volatile uint32_t *addr) uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) void __CLREX(void) uint32_t __RRX(uint32_t value) uint8_t __LDRBT(volatile uint8_t *addr) uint16_t __LDRHT(volatile uint16_t *addr) uint32_t __LDRT(volatile uint32_t *addr) void __STRBT(uint8_t value, volatile uint8_t *addr) void __STRHT(uint16_t value, volatile uint16_t *addr) void __STRT(uint32_t value, volatile uint32_t *addr) uint32_t __SADD8(uint32_t op1, uint32_t op2) uint32_t __QADD8(uint32_t op1, uint32_t op2) uint32_t __SHADD8(uint32_t op1, uint32_t op2) uint32_t __UADD8(uint32_t op1, uint32_t op2) uint32_t __UQADD8(uint32_t op1, uint32_t op2) uint32_t __UHADD8(uint32_t op1, uint32_t op2) uint32_t __SSUB8(uint32_t op1, uint32_t op2) uint32_t __QSUB8(uint32_t op1, uint32_t op2) uint32_t __SHSUB8(uint32_t op1, uint32_t op2) uint32_t __USUB8(uint32_t op1, uint32_t op2) uint32_t __UQSUB8(uint32_t op1, uint32_t op2) uint32_t __UHSUB8(uint32_t op1, uint32_t op2) uint32_t __SADD16(uint32_t op1, uint32_t op2) uint32_t __QADD16(uint32_t op1, uint32_t op2) uint32_t __SHADD16(uint32_t op1, uint32_t op2) uint32_t __UADD16(uint32_t op1, uint32_t op2) uint32_t __UQADD16(uint32_t op1, uint32_t op2) uint32_t __UHADD16(uint32_t op1, uint32_t op2) uint32_t __SSUB16(uint32_t op1, uint32_t op2) uint32_t __QSUB16(uint32_t op1, uint32_t op2) uint32_t __SHSUB16(uint32_t op1, uint32_t op2) uint32_t __USUB16(uint32_t op1, uint32_t op2) uint32_t __UQSUB16(uint32_t op1, uint32_t op2) uint32_t __UHSUB16(uint32_t op1, uint32_t op2) uint32_t __SASX(uint32_t op1, uint32_t op2) uint32_t __QASX(uint32_t op1, uint32_t op2) uint32_t __SHASX(uint32_t op1, uint32_t op2) uint32_t __UASX(uint32_t op1, uint32_t op2) uint32_t __UQASX(uint32_t op1, uint32_t op2) uint32_t __UHASX(uint32_t op1, uint32_t op2) uint32_t __SSAX(uint32_t op1, uint32_t op2) uint32_t __QSAX(uint32_t op1, uint32_t op2) uint32_t __SHSAX(uint32_t op1, uint32_t op2) uint32_t __USAX(uint32_t op1, uint32_t op2) uint32_t __UQSAX(uint32_t op1, uint32_t op2) uint32_t __UHSAX(uint32_t op1, uint32_t op2) uint32_t __USAD8(uint32_t op1, uint32_t op2) uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) uint32_t __UXTB16(uint32_t op1) uint32_t __UXTAB16(uint32_t op1, uint32_t op2) uint32_t __SXTB16(uint32_t op1) uint32_t __SXTAB16(uint32_t op1, uint32_t op2) uint32_t __SMUAD (uint32_t op1, uint32_t op2) uint32_t __SMUADX (uint32_t op1, uint32_t op2) uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) uint32_t __SMUSD (uint32_t op1, uint32_t op2) uint32_t __SMUSDX (uint32_t op1, uint32_t op2) uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) uint32_t __SEL (uint32_t op1, uint32_t op2) int32_t __QADD( int32_t op1, int32_t op2) int32_t __QSUB( int32_t op1, int32_t op2) uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
 |
| SDK Libraries | components\libraries\serial\nrf_serial.c |
nrf_serial_write(), serial_tx() |
| SDK Legacy Drivers | integration\nrfx\legacy\nrf_drv_uart.h |
nrf_drv_uart_tx() |
| SDK Peripheral Drivers | modules\nrfx\drivers\include\nrfx_uart.h |
nrfx_uart_tx() |
| SDK Glue to CMSIS/NVIC | integration\nrfx\nrfx_glue.h |
NRFX_IRQ_ENABLE() |
| CMSIS/NVIC | components\toolchain\cmsis\include\core_cm4.h |
nrf_drv_uart_tx() |
| SDK HAL | modules\nrfx\hal\nrf_uart.h |
nrf_uart_txd_set() |
| nRF52 Registers | modules\nrfx\mdk\nrf52.h |
NRF_UART_Type |
├── components
│ ├── 802_15_4
│ ├── ant
│ │ ├── ant_channel_config
│ │ ├── ant_encryption
│ │ ├── ant_fs
│ │ ├── ant_key_manager
│ │ ├── ant_profiles
│ │ ├── ant_search_config
│ │ └── ant_state_indicator
│ ├── ble
│ │ ├── ble_advertising
│ │ ├── ble_db_discovery
│ │ ├── ble_dtm
│ │ ├── ble_link_ctx_manager
│ │ ├── ble_racp
│ │ ├── ble_radio_notification
│ │ ├── ble_services
│ │ ├── common
│ │ ├── nrf_ble_gatt
│ │ ├── nrf_ble_qwr
│ │ ├── nrf_ble_scan
│ │ └── peer_manager
│ ├── boards
│ ├── drivers_ext (Sensors / Actuators)
│ ├── drivers_nrf
│ │ ├── nrf_soc_nosd
│ │ ├── radio_config
│ │ ├── sdio
│ │ ├── spi_master
│ │ ├── twi_master
│ │ └── usbd
│ ├── iot
│ │ ├── background_dfu
│ │ ├── ble_6lowpan
│ │ ├── coap
│ │ ├── common
│ │ ├── context_manager
│ │ ├── errno
│ │ ├── iot_file
│ │ ├── iot_timer
│ │ ├── ipv6_parse
│ │ ├── ipv6_stack
│ │ ├── lwm2m
│ │ ├── medium
│ │ ├── mqtt
│ │ └── socket
│ ├── libraries
│ │ ├── atomic
│ │ ├── atomic_fifo
│ │ ├── atomic_flags
│ │ ├── balloc
│ │ ├── block_dev
│ │ ├── bootloader
│ │ ├── bsp
│ │ ├── button
│ │ ├── cli
│ │ ├── crc16
│ │ ├── crc32
│ │ ├── crypto
│ │ ├── csense
│ │ ├── csense_drv
│ │ ├── delay
│ │ ├── ecc
│ │ ├── experimental_libuarte
│ │ ├── experimental_section_vars
│ │ ├── experimental_task_manager
│ │ ├── fds
│ │ ├── fifo
│ │ ├── fstorage
│ │ ├── gfx
│ │ ├── gpiote
│ │ ├── hardfault
│ │ ├── hci
│ │ ├── led_softblink
│ │ ├── log
│ │ ├── low_power_pwm
│ │ ├── mem_manager
│ │ ├── memobj
│ │ ├── mpu
│ │ ├── mutex
│ │ ├── pwm
│ │ ├── pwr_mgmt
│ │ ├── queue
│ │ ├── ringbuf
│ │ ├── scheduler
│ │ ├── sdcard
│ │ ├── sensorsim
│ │ ├── serial (SDK Libraries) -> nrf_serial_write()
│ │ ├── sha256
│ │ ├── simple_timer
│ │ ├── slip
│ │ ├── sortlist
│ │ ├── spi_mngr
│ │ ├── stack_guard
│ │ ├── stack_info
│ │ ├── strerror
│ │ ├── svc
│ │ ├── timer
│ │ ├── twi_mngr
│ │ ├── twi_sensor
│ │ ├── uart
│ │ ├── usbd
│ │ └── util
│ ├── nfc
│ ├── proprietary_rf
│ │ ├── esb
│ │ └── gzll
│ ├── serialization
│ │ ├── application
│ │ ├── common
│ │ └── connectivity
│ ├── softdevice
│ │ ├── common
│ │ ├── mbr
│ │ │ ├── nrf52810
│ │ │ ├── nrf52832
│ │ │ └── nrf52840
│ │ ├── s112
│ │ ├── s132
│ │ ├── s140
│ │ └── s212
│ └── toolchain
│ ├── arm
│ ├── cmsis
│ ├── gcc
│ └── iar
├── config
│ ├── nrf52810
│ ├── nrf52832
│ └── nrf52840
├── documentation
├── external
│ ├── cifra_AES128-EAX
│ ├── cJSON
│ ├── fatfs
│ ├── fnmatch
│ ├── fprintf
│ ├── freertos
│ ├── infineon
│ ├── lwip
│ ├── mbedtls
│ ├── micro-ecc
│ ├── nano
│ ├── nano-pb
│ ├── nfc_adafruit_library
│ ├── nrf_cc310
│ ├── nrf_cc310_bl
│ ├── nrf_oberon
│ ├── nrf_tls
│ │ └── mbedtls
│ ├── protothreads
│ ├── segger_rt
│ ├── thedotfactory_fonts
│ └── utf_converter
├── external_tools
├── integration
│ └── nrfx
│ └── legacy (SDK Legacy Drivers) -> nrf_drv_uart_tx()
└── modules
└── nrfx
├── doc
├── drivers (SDK Peripheral Drivers) -> nrfx_uart_tx()
├── hal (SDK HAL) -> nrf_uart_txd_set()
│ -> nrf_gpio_cfg_output()
├── mdk
└── soc
WFE/WFI instruction stop/decrease clock frequencynrf52, use Systick or RTC?
RTC with 1ms resolution – YYYY-MM-DD HH:MM:SS.mmm
nRF52 SysTick Clock Source
SysTick timer on nRF52 fires 1/5 as often as expected
WFI instruction slowing down SYStick interrupt
How to set Systick timer in nRF52
Power Off mode
nrf.h nrf_peripherals.h nrf51.h nrf51_bitfields.h nrf51_deprecated.h nrf51_peripherals.h nrf51_to_nrf52.h nrf51_to_nrf52810.h nrf51_to_nrf52840.h nrf51422_peripherals.h nrf51801_peripherals.h nrf51802_peripherals.h nrf51822_peripherals.h nrf51824_peripherals.h nrf52.h nrf52_bitfields.h nrf52_name_change.h nrf52_to_nrf52810.h nrf52_to_nrf52840.h nrf52810.h nrf52810_bitfields.h nrf52810_peripherals.h nrf52832_peripherals.h nrf52840.h nrf52840_bitfields.h nrf52840_peripherals.h nrf51.svd nrf52.svd nrf52810.svd nrf52840.svd nrf_common.ld nrf51_common.ld nrf51_xxaa.ld nrf51_xxab.ld nrf51_xxac.ld nrf51801_xxab.ld nrf52_common.ld nrf52_xxaa.ld nrf52810_xxaa.ld nrf52832_xxab.ld nrf52840_xxaa.ld
ble_ancs_c Apple Notification Service client ble_ans_c Alert Notification Service Client ble_bas Battery Service ble_bas_c Battery Service Client ble_bps Blood Pressure Service ble_cscs Cycling Speed and Cadence Service ble_cts_c Current Time Service client ble_dfu Buttonless DFU Service ble_dis Device Information Service ble_dis_c Device Information Service Client ble_escs Eddystone Configuration Service ble_gls Glucose Service ble_hids Human Interface Device Service ble_hrs Heart Rate Service ble_hrs_c Heart Rate Service Client ble_hts Health Thermometer Service ble_ias Immediate Alert Service ble_ias_c Immediate Alert Service Client ble_ipsp Internet Protocol Support Profile ble_lbs LED Button Service Server ble_lbs_c LED Button Service Client ble_lls Link Loss Service ble_nus Nordic UART Service ble_nus_c Nordic UART Service Client ble_rscs Running Speed and Cadence Service ble_rscs_c Running Speed and Cadence Service Client ble_tps TX Power Service eddystone experimental_ble_lns Location and Navigation Service experimental_ble_ots Object Transfer Service experimental_gatts_c GATT Service Client experimental_nrf_ble_cgms Continuous Glucose Monitoring Service experimental_nrf_ble_ots_c Object Transfer Service Client nrf_ble_bms Bond Management Service
<info> app: Current Time service client started. <debug> app: pm_whitelist_get returns 0 addr in whitelist and 0 irk whitelist <info> app: Fast advertising <debug> app: pm_whitelist_get returns 0 addr in whitelist and 0 irk whitelist <info> app: Slow advertising <debug> ble_cts_c: BLE event handler called with event 0x26 <debug> ble_cts_c: BLE event handler called with event 0x10 <info> app: Connected. <debug> ble_cts_c: BLE event handler called with event 0x12 <debug> ble_cts_c: BLE event handler called with event 0x12 <debug> ble_cts_c: BLE event handler called with event 0x12 <debug> ble_cts_c: BLE event handler called with event 0x19 <debug> app: pm_whitelist_get returns 0 addr in whitelist and 0 irk whitelist <info> app: Fast advertising <debug> ble_cts_c: BLE event handler called with event 0x11 <info> app: Disconnected. <debug> app: pm_whitelist_get returns 0 addr in whitelist and 0 irk whitelist <info> app: Slow advertising <debug> ble_cts_c: BLE event handler called with event 0x26
sd_power_system_off() doesn’t power off: it’s in Debug Mode!!
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sd_power_system_off returns immediately and forces reset
Why does nRF52 hrs sdk11 example sd_power_off return 6?
Problem with emulated System OFF mode with NRF52
/* components/softdevice/s132/headers/nrf_error.h */ /* SoC error base */ #define NRF_ERROR_SOC_BASE_NUM (0x2000) /* components/softdevice/s132/headers/nrf_error_soc.h */ /* Power off should not return */ #define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 6) /* components/softdevice/s132/headers/nrf_soc.h */ /**@brief Puts the chip in System OFF mode. * * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN */ SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void));
Installing automatically
Installing manually
Building and programming an application
nRF Connect for Desktop
nRF Connect for Desktop Download
Developing with Zephyr – Installing west
Nordic: West (Zephyr’s meta-tool) – Moving to West
Software Development Kit > nRF5 SDK v17.1.0 > Libraries > Logger module (nRF5 SDK v17.1.0)
Software Development Kit > nRF5 SDK v17.1.0 > API Reference > SDK common libraries > Logger module (nRF5 SDK v17.1.0)
UART driver – legacy layer (nRF5 SDK v17.1.0)
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My device is freezing and restarting
Understand UART, UARTE and getting it to work with PPI
UART and UARTE difference
How to properly switch between UART pins and baud rates with nRF52 (UARTE)
No, sorry if that wasn’t clear. UARTE is Universal asynchronous receiver/transmitter (UART) with EasyDMA, so if you don’t want DMA you will have to use the UART peripheral.
| UART library, Serial Port library | |
| UART driver | provides APIs on a higher level than the HAL |
| Hardware Abstraction Layer (HAL) | simplyfy reading and writing the registers |
| UART peripheral | writing to and reading from the registers (UART = legacy peripherals, UARTE = peripherals using EasyDMA) |
*** Booting Zephyr OS build v2.7.99-ncs1-1 *** Bluetooth initialized Advertising successfully started Indicate VND attr 0x2ba80 (UUID 12345678-1234-5678-1234-56789abcdef1) [00:00:02.145,019] <inf> fs_nvs: 6 Sectors of 4096 bytes [00:00:02.145,050] <inf> fs_nvs: alloc wra: 0, fb0 [00:00:02.145,050] <inf> fs_nvs: data wra: 0, 5c [00:00:02.146,728] <inf> bt_hci_core: HW Platform: Nordic Semiconductor (0x0002) [00:00:02.146,759] <inf> bt_hci_core: HW Variant: nRF52x (0x0002) [00:00:02.146,759] <inf> bt_hci_core: Firmware: Standard Bluetooth controller (0x00) Version 2.7 Build 99 [00:00:02.147,094] <inf> bt_hci_core: No ID address. App must call settings_load() [00:00:06.002,380] <inf> bt_hci_core: Identity: ED:CA:07:92:F1:2E (random) [00:00:06.002,410] <inf> bt_hci_core: HCI: version 5.3 (0x0c) revision 0x0000, manufacturer 0x05f1 [00:00:06.002,410] <inf> bt_hci_core: LMP: version 5.3 (0x0c) subver 0xffff Updated MTU: TX: 23 RX: 23 bytes Connected Passkey for 4E:57:AA:0F:73:AE (random): 175962 [00:01:33.121,582] <inf> hrs: HRS notifications enabled [00:02:13.982,208] <inf> bas: BAS Notifications enabled Disconnected (reason 0x13) [00:04:31.009,704] <inf> bas: BAS Notifications disabled [00:04:31.009,765] <inf> hrs: HRS notifications disabled
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Ellisys Bluetooth Video Series (Playlist)