Standard

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_unsigned.all;
use IEEE.math_real.all;
use IEEE.math_complex.all;

library STD;
use STD.textio;

VHDL standard packages and types

• ‘X’ usually is caused by two statements driving the same signal in opposite directions,i.e., ‘0’ and ‘1’
• ‘Z’ is used to build a tri stated output/input
• ‘L’ and ‘H’ are used to model a pulldown or pullup respectively
• ‘-‘ is used in comparisons when you don’t care about certain bits in a vector

stackoverflow: std_logic in VHDL

Wikipedia

VHDL
Four-valued logic (en)
IEEE 1164 (en)
Dataflow programming (en)