{"id":8995,"date":"2018-12-30T15:54:39","date_gmt":"2018-12-30T15:54:39","guid":{"rendered":"http:\/\/blog.bachi.net\/?p=8995"},"modified":"2018-12-30T16:35:17","modified_gmt":"2018-12-30T16:35:17","slug":"nrf5-sdk-cmsis-nvic-part","status":"publish","type":"post","link":"https:\/\/blog.bachi.net\/?p=8995","title":{"rendered":"nRF5 SDK: CMSIS \/ NVIC Part"},"content":{"rendered":"<table class=\"doxtable\">\n<tbody>\n<tr>\n<th align=\"left\">Header File <\/th>\n<th align=\"left\">Processor  <\/th>\n<\/tr>\n<tr>\n<td align=\"left\">core_cm0.h <\/td>\n<td align=\"left\">for the Cortex-M0 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_cm0plus.h <\/td>\n<td align=\"left\">for the Cortex-M0+ processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_cm3.h <\/td>\n<td align=\"left\">for the Cortex-M3 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_cm4.h <\/td>\n<td align=\"left\">for the Cortex-M4 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_cm7.h <\/td>\n<td align=\"left\">for the Cortex-M7 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_cm23.h <\/td>\n<td align=\"left\">for the Cortex-M23 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_cm33.h <\/td>\n<td align=\"left\">for the Cortex-M33 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_sc000.h <\/td>\n<td align=\"left\">for the SecurCore SC000 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_sc300.h <\/td>\n<td align=\"left\">for the SecurCore SC300 processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_armv8mbl.h <\/td>\n<td align=\"left\">for the Armv8-M Baseline processor <\/td>\n<\/tr>\n<tr>\n<td align=\"left\">core_armv8mml.h <\/td>\n<td align=\"left\">for the Armv8-M Mainline processor <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<pre class=\"brush: plain; title: Types; notranslate\" title=\"Types\">\r\nAPSR_Type\r\nIPSR_Type\r\nxPSR_Type\r\nCONTROL_Type\r\nNVIC_Type\r\nSCB_Type\r\nSCnSCB_Type\r\nSysTick_Type\r\nITM_Type\r\nDWT_Type\r\nTPI_Type\r\nMPU_Type\r\nFPU_Type\r\nCoreDebug_Type\r\n<\/pre>\n<pre class=\"brush: cpp; title: modules\nrfxmdk\nrf52.h; notranslate\" title=\"modules\nrfxmdk\nrf52.h\">\r\ntypedef enum {\r\n\/* ===  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== *\/\r\n  Reset_IRQn                = -15,              \/*!&lt; -15 Reset Vector, invoked on          *\/\r\n                                                \/*       Power up and warm reset           *\/\r\n  NonMaskableInt_IRQn       = -14,              \/*!&lt; -14 Non maskable Interrupt,           *\/\r\n                                                \/*       cannot be stopped or preempted    *\/\r\n  HardFault_IRQn            = -13,              \/*!&lt; -13 Hard Fault, all classes of Fault  *\/\r\n  MemoryManagement_IRQn     = -12,              \/*!&lt; -12 Memory Management, MPU mismatch,  *\/\r\n                                                \/*       including Access Violation        *\/\r\n                                                \/*       and No Match                      *\/\r\n  BusFault_IRQn             = -11,              \/*!&lt; -11 Bus Fault, Pre-Fetch-,            *\/\r\n                                                \/*       Memory Access Fault,              *\/\r\n                                                \/*       other address\/memory              *\/\r\n                                                \/*       related Fault                     *\/\r\n  UsageFault_IRQn           = -10,              \/*!&lt; -10 Usage Fault, i.e.                 *\/\r\n                                                \/*       Undef Instruction,                *\/\r\n                                                \/*       Illegal State Transition          *\/\r\n  SVCall_IRQn               =  -5,              \/*!&lt;  -5 System Service Call via           *\/\r\n                                                \/*      SVC instruction                    *\/\r\n  DebugMonitor_IRQn         =  -4,              \/*!&lt;  -4 Debug Monitor                     *\/\r\n  PendSV_IRQn               =  -2,              \/*!&lt;  -2 Pendable request for SV           *\/\r\n  SysTick_IRQn              =  -1,              \/*!&lt;  -1 System Tick Timer                 *\/\r\n\/* ===  nrf52 Specific Interrupt Numbers  ================================================ *\/\r\n  POWER_CLOCK_IRQn          =   0,              \/*!&lt;  0 POWER_CLOCK                        *\/\r\n  RADIO_IRQn                =   1,              \/*!&lt;  1 RADIO                              *\/\r\n  UARTE0_UART0_IRQn         =   2,              \/*!&lt;  2 UARTE0_UART0                       *\/\r\n  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,  \/*!&lt;  3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0  *\/\r\n  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,  \/*!&lt;  4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1  *\/\r\n  NFCT_IRQn                 =   5,              \/*!&lt;  5 NFCT                               *\/\r\n  GPIOTE_IRQn               =   6,              \/*!&lt;  6 GPIOTE                             *\/\r\n  SAADC_IRQn                =   7,              \/*!&lt;  7 SAADC                              *\/\r\n  TIMER0_IRQn               =   8,              \/*!&lt;  8 TIMER0                             *\/\r\n  TIMER1_IRQn               =   9,              \/*!&lt;  9 TIMER1                             *\/\r\n  TIMER2_IRQn               =  10,              \/*!&lt; 10 TIMER2                             *\/\r\n  RTC0_IRQn                 =  11,              \/*!&lt; 11 RTC0                               *\/\r\n  TEMP_IRQn                 =  12,              \/*!&lt; 12 TEMP                               *\/\r\n  RNG_IRQn                  =  13,              \/*!&lt; 13 RNG                                *\/\r\n  ECB_IRQn                  =  14,              \/*!&lt; 14 ECB                                *\/\r\n  CCM_AAR_IRQn              =  15,              \/*!&lt; 15 CCM_AAR                            *\/\r\n  WDT_IRQn                  =  16,              \/*!&lt; 16 WDT                                *\/\r\n  RTC1_IRQn                 =  17,              \/*!&lt; 17 RTC1                               *\/\r\n  QDEC_IRQn                 =  18,              \/*!&lt; 18 QDEC                               *\/\r\n  COMP_LPCOMP_IRQn          =  19,              \/*!&lt; 19 COMP_LPCOMP                        *\/\r\n  SWI0_EGU0_IRQn            =  20,              \/*!&lt; 20 SWI0_EGU0                          *\/\r\n  SWI1_EGU1_IRQn            =  21,              \/*!&lt; 21 SWI1_EGU1                          *\/\r\n  SWI2_EGU2_IRQn            =  22,              \/*!&lt; 22 SWI2_EGU2                          *\/\r\n  SWI3_EGU3_IRQn            =  23,              \/*!&lt; 23 SWI3_EGU3                          *\/\r\n  SWI4_EGU4_IRQn            =  24,              \/*!&lt; 24 SWI4_EGU4                          *\/\r\n  SWI5_EGU5_IRQn            =  25,              \/*!&lt; 25 SWI5_EGU5                          *\/\r\n  TIMER3_IRQn               =  26,              \/*!&lt; 26 TIMER3                             *\/\r\n  TIMER4_IRQn               =  27,              \/*!&lt; 27 TIMER4                             *\/\r\n  PWM0_IRQn                 =  28,              \/*!&lt; 28 PWM0                               *\/\r\n  PDM_IRQn                  =  29,              \/*!&lt; 29 PDM                                *\/\r\n  MWU_IRQn                  =  32,              \/*!&lt; 32 MWU                                *\/\r\n  PWM1_IRQn                 =  33,              \/*!&lt; 33 PWM1                               *\/\r\n  PWM2_IRQn                 =  34,              \/*!&lt; 34 PWM2                               *\/\r\n  SPIM2_SPIS2_SPI2_IRQn     =  35,              \/*!&lt; 35 SPIM2_SPIS2_SPI2                   *\/\r\n  RTC2_IRQn                 =  36,              \/*!&lt; 36 RTC2                               *\/\r\n  I2S_IRQn                  =  37,              \/*!&lt; 37 I2S                                *\/\r\n  FPU_IRQn                  =  38               \/*!&lt; 38 FPU                                *\/\r\n} IRQn_Type;\r\n<\/pre>\n<pre class=\"brush: cpp; title: components\/toolchain\/cmsis\/include\/core_cm4.h; notranslate\" title=\"components\/toolchain\/cmsis\/include\/core_cm4.h\">\r\n\/* Memory mapping of Cortex-M4 Hardware *\/\r\n#define SCS_BASE            (0xE000E000UL)                            \/*!&lt; System Control Space Base Address *\/\r\n#define ITM_BASE            (0xE0000000UL)                            \/*!&lt; ITM Base Address *\/\r\n#define DWT_BASE            (0xE0001000UL)                            \/*!&lt; DWT Base Address *\/\r\n#define TPI_BASE            (0xE0040000UL)                            \/*!&lt; TPI Base Address *\/\r\n#define CoreDebug_BASE      (0xE000EDF0UL)                            \/*!&lt; Core Debug Base Address *\/\r\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    \/*!&lt; SysTick Base Address *\/\r\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    \/*!&lt; NVIC Base Address *\/\r\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    \/*!&lt; System Control Block Base Address *\/\r\n\r\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   \/*!&lt; System control Register not in SCB *\/\r\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   \/*!&lt; SCB configuration struct *\/\r\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   \/*!&lt; SysTick configuration struct *\/\r\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   \/*!&lt; NVIC configuration struct *\/\r\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   \/*!&lt; ITM configuration struct *\/\r\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   \/*!&lt; DWT configuration struct *\/\r\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   \/*!&lt; TPI configuration struct *\/\r\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   \/*!&lt; Core Debug configuration struct *\/\r\n\r\ntypedef struct\r\n{\r\n  __IOM uint32_t ISER&#x5B;8U];               \/*!&lt; Offset: 0x000 (R\/W)  Interrupt Set Enable Register *\/\r\n        uint32_t RESERVED0&#x5B;24U];\r\n  __IOM uint32_t ICER&#x5B;8U];               \/*!&lt; Offset: 0x080 (R\/W)  Interrupt Clear Enable Register *\/\r\n        uint32_t RSERVED1&#x5B;24U];\r\n  __IOM uint32_t ISPR&#x5B;8U];               \/*!&lt; Offset: 0x100 (R\/W)  Interrupt Set Pending Register *\/\r\n        uint32_t RESERVED2&#x5B;24U];\r\n  __IOM uint32_t ICPR&#x5B;8U];               \/*!&lt; Offset: 0x180 (R\/W)  Interrupt Clear Pending Register *\/\r\n        uint32_t RESERVED3&#x5B;24U];\r\n  __IOM uint32_t IABR&#x5B;8U];               \/*!&lt; Offset: 0x200 (R\/W)  Interrupt Active bit Register *\/\r\n        uint32_t RESERVED4&#x5B;56U];\r\n  __IOM uint8_t  IP&#x5B;240U];               \/*!&lt; Offset: 0x300 (R\/W)  Interrupt Priority Register (8Bit wide) *\/\r\n        uint32_t RESERVED5&#x5B;644U];\r\n  __OM  uint32_t STIR;                   \/*!&lt; Offset: 0xE00 ( \/W)  Software Trigger Interrupt Register *\/\r\n}  NVIC_Type;\r\n\r\ntypedef struct\r\n{\r\n  __IOM uint32_t CTRL;                   \/*!&lt; Offset: 0x000 (R\/W)  SysTick Control and Status Register *\/\r\n  __IOM uint32_t LOAD;                   \/*!&lt; Offset: 0x004 (R\/W)  SysTick Reload Value Register *\/\r\n  __IOM uint32_t VAL;                    \/*!&lt; Offset: 0x008 (R\/W)  SysTick Current Value Register *\/\r\n  __IM  uint32_t CALIB;                  \/*!&lt; Offset: 0x00C (R\/ )  SysTick Calibration Register *\/\r\n} SysTick_Type;\r\n\r\nvoid     NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r\nuint32_t NVIC_GetPriorityGrouping(void)\r\nvoid     NVIC_EnableIRQ(IRQn_Type IRQn)\r\nvoid     NVIC_DisableIRQ(IRQn_Type IRQn)\r\nuint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r\nvoid     NVIC_SetPendingIRQ(IRQn_Type IRQn)\r\nvoid     NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r\nuint32_t NVIC_GetActive(IRQn_Type IRQn)\r\nvoid     NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r\nuint32_t NVIC_GetPriority(IRQn_Type IRQn)\r\nuint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r\nvoid     NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r\nvoid     NVIC_SystemReset(void)\r\n\r\nuint32_t SysTick_Config(uint32_t ticks)\r\n\r\nuint32_t ITM_SendChar (uint32_t ch)\r\nint32_t  ITM_ReceiveChar (void)\r\nint32_t  ITM_CheckChar (void)\r\n<\/pre>\n<pre class=\"brush: cpp; title: components\/toolchain\/cmsis\/include\/cmsis_gcc.h; notranslate\" title=\"components\/toolchain\/cmsis\/include\/cmsis_gcc.h\">\r\nvoid     __enable_irq(void)\r\nvoid     __disable_irq(void)\r\nuint32_t __get_CONTROL(void)\r\nvoid     __set_CONTROL(uint32_t control)\r\nuint32_t __get_IPSR(void)\r\nuint32_t __get_APSR(void)\r\nuint32_t __get_xPSR(void)\r\nuint32_t __get_PSP(void)\r\nvoid     __set_PSP(uint32_t topOfProcStack)\r\nuint32_t __get_MSP(void)\r\nvoid     __set_MSP(uint32_t topOfMainStack)\r\nuint32_t __get_PRIMASK(void)\r\nvoid     __set_PRIMASK(uint32_t priMask)\r\nvoid     __enable_fault_irq(void)\r\nvoid     __disable_fault_irq(void)\r\nuint32_t __get_BASEPRI(void)\r\nvoid     __set_BASEPRI(uint32_t value)\r\nvoid     __set_BASEPRI_MAX(uint32_t value)\r\nuint32_t __get_FAULTMASK(void)\r\nvoid     __set_FAULTMASK(uint32_t faultMask)\r\nuint32_t __get_FPSCR(void)\r\nvoid     __set_FPSCR(uint32_t fpscr)\r\n\r\nvoid     __NOP(void)\r\nvoid     __WFI(void)\r\nvoid     __WFE(void)\r\nvoid     __SEV(void)\r\nvoid     __ISB(void)\r\nvoid     __DSB(void)\r\nvoid     __DMB(void)\r\nuint32_t __REV(uint32_t value)\r\nuint32_t __REV16(uint32_t value)\r\n int32_t __REVSH(int32_t value)\r\nuint32_t __ROR(uint32_t op1, uint32_t op2)\r\nuint32_t __RBIT(uint32_t value)\r\nuint8_t  __LDREXB(volatile uint8_t *addr)\r\nuint16_t __LDREXH(volatile uint16_t *addr)\r\nuint32_t __LDREXW(volatile uint32_t *addr)\r\nuint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r\nuint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r\nuint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r\nvoid     __CLREX(void)\r\nuint32_t __RRX(uint32_t value)\r\nuint8_t  __LDRBT(volatile uint8_t *addr)\r\nuint16_t __LDRHT(volatile uint16_t *addr)\r\nuint32_t __LDRT(volatile uint32_t *addr)\r\nvoid     __STRBT(uint8_t value, volatile uint8_t *addr)\r\nvoid     __STRHT(uint16_t value, volatile uint16_t *addr)\r\nvoid     __STRT(uint32_t value, volatile uint32_t *addr)\r\n\r\nuint32_t __SADD8(uint32_t op1, uint32_t op2)\r\nuint32_t __QADD8(uint32_t op1, uint32_t op2)\r\nuint32_t __SHADD8(uint32_t op1, uint32_t op2)\r\nuint32_t __UADD8(uint32_t op1, uint32_t op2)\r\nuint32_t __UQADD8(uint32_t op1, uint32_t op2)\r\nuint32_t __UHADD8(uint32_t op1, uint32_t op2)\r\nuint32_t __SSUB8(uint32_t op1, uint32_t op2)\r\nuint32_t __QSUB8(uint32_t op1, uint32_t op2)\r\nuint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r\nuint32_t __USUB8(uint32_t op1, uint32_t op2)\r\nuint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r\nuint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r\nuint32_t __SADD16(uint32_t op1, uint32_t op2)\r\nuint32_t __QADD16(uint32_t op1, uint32_t op2)\r\nuint32_t __SHADD16(uint32_t op1, uint32_t op2)\r\nuint32_t __UADD16(uint32_t op1, uint32_t op2)\r\nuint32_t __UQADD16(uint32_t op1, uint32_t op2)\r\nuint32_t __UHADD16(uint32_t op1, uint32_t op2)\r\nuint32_t __SSUB16(uint32_t op1, uint32_t op2)\r\nuint32_t __QSUB16(uint32_t op1, uint32_t op2)\r\nuint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r\nuint32_t __USUB16(uint32_t op1, uint32_t op2)\r\nuint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r\nuint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r\nuint32_t __SASX(uint32_t op1, uint32_t op2)\r\nuint32_t __QASX(uint32_t op1, uint32_t op2)\r\nuint32_t __SHASX(uint32_t op1, uint32_t op2)\r\nuint32_t __UASX(uint32_t op1, uint32_t op2)\r\nuint32_t __UQASX(uint32_t op1, uint32_t op2)\r\nuint32_t __UHASX(uint32_t op1, uint32_t op2)\r\nuint32_t __SSAX(uint32_t op1, uint32_t op2)\r\nuint32_t __QSAX(uint32_t op1, uint32_t op2)\r\nuint32_t __SHSAX(uint32_t op1, uint32_t op2)\r\nuint32_t __USAX(uint32_t op1, uint32_t op2)\r\nuint32_t __UQSAX(uint32_t op1, uint32_t op2)\r\nuint32_t __UHSAX(uint32_t op1, uint32_t op2)\r\nuint32_t __USAD8(uint32_t op1, uint32_t op2)\r\nuint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r\nuint32_t __UXTB16(uint32_t op1)\r\nuint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r\nuint32_t __SXTB16(uint32_t op1)\r\nuint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r\nuint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r\nuint32_t __SMUADX (uint32_t op1, uint32_t op2)\r\nuint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r\nuint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r\nuint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r\nuint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\nuint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r\nuint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r\nuint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r\nuint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r\nuint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r\nuint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r\nuint32_t __SEL  (uint32_t op1, uint32_t op2)\r\n int32_t __QADD( int32_t op1,  int32_t op2)\r\n int32_t __QSUB( int32_t op1,  int32_t op2)\r\nuint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r\n<\/pre>\n","protected":false},"excerpt":{"rendered":"<p>Header File Processor core_cm0.h for the Cortex-M0 processor core_cm0plus.h for the Cortex-M0+ processor core_cm3.h for the Cortex-M3 processor core_cm4.h for the Cortex-M4 processor core_cm7.h for the Cortex-M7 processor core_cm23.h for the Cortex-M23 processor core_cm33.h for the Cortex-M33 processor core_sc000.h for the SecurCore SC000 processor core_sc300.h for the SecurCore SC300 processor core_armv8mbl.h for the Armv8-M Baseline [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-8995","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/8995","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=8995"}],"version-history":[{"count":5,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/8995\/revisions"}],"predecessor-version":[{"id":9000,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/8995\/revisions\/9000"}],"wp:attachment":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=8995"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=8995"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=8995"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}