{"id":6296,"date":"2017-05-31T13:12:57","date_gmt":"2017-05-31T13:12:57","guid":{"rendered":"http:\/\/blog.bachi.net\/?p=6296"},"modified":"2023-02-21T14:17:58","modified_gmt":"2023-02-21T14:17:58","slug":"esp32","status":"publish","type":"post","link":"https:\/\/blog.bachi.net\/?p=6296","title":{"rendered":"ESP32"},"content":{"rendered":"<p><a href=\"https:\/\/www.espressif.com\/sites\/default\/files\/documentation\/espressif_products_ordering_information_en.pdf\">Espressif &#8211; Product Ordering Information<\/a><br \/>\n<a href=\"https:\/\/esp32.com\/viewtopic.php?t=8509\">Difference between ESP32-WROVER and ESP32-WROVER-B<\/a><\/p>\n<p><a href=\"https:\/\/esp-idf.readthedocs.io\/en\/v2.0\/index.html\">ESP-IDF Programming Guide<\/a>, v2<br \/>\n<a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/\">ESP-IDF Programming Guide<\/a>, latest<br \/>\n<a href=\"https:\/\/hackaday.com\/2016\/09\/15\/esp32-hands-on-awesome-promise\/\">hackaday ESP32 Hands-On: Awesome Promise<\/a><\/p>\n<p><a href=\"https:\/\/twitter.com\/ESP32net?lang=de\">Twitter: ESP32.net<\/a>, Projekte ansehen<\/p>\n<p>Tensilica(Cadence Design Systems) Xtensa (configurable cores)<\/p>\n<blockquote><p>Das Espressif IoT Development Framework ist ein auf FreeRTOS und lwIP basiertes Entwicklungssystem f\u00fcr den ESP32.<\/p><\/blockquote>\n<p><a href=\"https:\/\/www.esp32.com\/viewtopic.php?t=1293\">ESP-IDF, multicore &#038; freeRTOS confusion<\/a><br \/>\nTo sum up my assumptions about ESP32 I make, when asking this question:<\/p>\n<ul>\n<li>ESP32 contains two identical cores, one is PRO_CPU and the second is APP_CPU.<\/li>\n<li>Application entry points on both CPUs (start_cpu0 and start_cpu1) are weak functions.<\/li>\n<li>However some useful parts of ESP-IDF are written or configured to use FreeRTOS synchronisation and locking primitives.<\/li>\n<li>ESP-IDF is build on top FreeRTOS. That means that handling of WiFi and other stuff is handled as RTOS task.<\/li>\n<li>ESP-IDF is the lowest-possible API officially supported<\/li>\n<\/ul>\n<p><a href=\"http:\/\/esp32.net\/\">The Internet of Things with ESP32<\/a><br \/>\n<a href=\"https:\/\/espressif.com\/en\/products\/hardware\/esp32\/overview\">ESP32 Overview<\/a><\/p>\n<p><!-- --><\/p>\n<h3>Download<\/h3>\n<p><a href=\"https:\/\/dl.espressif.com\/dl\/esp-idf\/\">ESP-IDF Windows Installer Download<\/a><br \/>\n<a href=\"https:\/\/docs.espressif.com\/projects\/esp-idf\/en\/latest\/esp32\/\">ESP-IDF Programming Guide<\/a><\/p>\n<h3>Installation<\/h3>\n<p><a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/get-started\/linux-setup.html\">Standard Setup of Toolchain for Linux<\/a><\/p>\n<pre class=\"brush: plain; title: Arduino; notranslate\" title=\"Arduino\">\r\nsudo usermod -a -G dialout $USER &amp;&amp; \\\r\nsudo apt-get install git wget make libncurses-dev \\\r\nflex bison gperf python python-serial &amp;&amp; \\\r\nwget https:\/\/bootstrap.pypa.io\/get-pip.py &amp;&amp; \\\r\nsudo python get-pip.py &amp;&amp; \\\r\nsudo pip install pyserial &amp;&amp; \\\r\nmkdir -p ~\/Arduino\/hardware\/espressif &amp;&amp; \\\r\ncd ~\/Arduino\/hardware\/espressif &amp;&amp; \\\r\ngit clone https:\/\/github.com\/espressif\/arduino-esp32.git esp32 &amp;&amp; \\\r\ncd esp32\/tools\/ &amp;&amp; \\\r\npython get.py\r\n<\/pre>\n<pre class=\"brush: plain; title: ESP-IDF; notranslate\" title=\"ESP-IDF\">\r\n\r\n<\/pre>\n<h3>Emulator \/ Simulator (QEMU)<\/h3>\n<p><a href=\"http:\/\/wiki.linux-xtensa.org\/index.php\/Xtensa_on_QEMU\">Xtensa on QEMU<\/a><br \/>\n<a href=\"http:\/\/wiki.qemu.org\/index.php\/Features\/Xtensa\">Features\/Xtensa<\/a><br \/>\nOlof Astrand <olof.astrand@gmail.com>\n<a href=\"https:\/\/github.com\/Ebiroll\/qemu_esp32\">github.com\/Ebiroll\/qemu_esp32<\/a>, Add tensilica esp32 cpu and a board to qemu and dump the rom to learn more about esp-idf <\/p>\n<h3>Shop<\/h3>\n<p><a href=\"https:\/\/de.aliexpress.com\/store\/product\/WEMOS-LOLIN32-V1-0-0-wifi-bluetooth-board-based-ESP-32-4MB-FLASH\/1331105_32808551116.html\">WEMOS LOLIN32 V1.0.0<\/a><\/p>\n<h3>Battery Jack \/ Akku Buchse<\/h3>\n<p>It has two jacks: one for a battery and one for an USB plug that can be used to charge the battery. The charging circuit is built around a TP5410 Lipo charger. One therefore would expect a standard LiPo cell connector on the board but the LiPo cell connector on the board is an XH2.54 connector, whereas most LiPo cells come with a JST-PH connector. Another disappointment was that it came with male headers only. Apparently it is thought this shield should come on top of every other possible shield.<\/p>\n<p>There is still no technical information but it seems possible to charge the battery from the micro USB port. The connector is not specified but it looks identical to that of the shield battery (presentation), connector JST XH2-2.54mm. The dedicated page of the Wiki is under construction.<\/p>\n<p>The Wemos LoLin32 has the particularity to propose a connector for LiPo battery. The connector is JST XH2-2.54mm. It has a key that prevents reverse polarity.<\/p>\n<p>La Wemos LoLin32 a la particularit\u00e9 de proposer un connecteur pour batterie LiPo. Le connecteur est de type JST XH2-2.54mm. Il dispose d\u2019un d\u00e9trompeur qui emp\u00eache l\u2019inversion de polarit\u00e9. <\/p>\n<h3>SourceCode<\/h3>\n<p><a href=\"https:\/\/github.com\/espressif\/esp-idf\">Espressif IoT Development Framework<\/a><br \/>\n<a href=\"https:\/\/github.com\/espressif\/esp-idf\/tree\/9b30f66\/examples\/get-started\/hello_world\">Hello World Example<\/a><br \/>\n<a href=\"https:\/\/github.com\/espressif\/arduino-esp32\">Arduino core for ESP32 WiFi chip<\/a><br \/>\n<a href=\"https:\/\/github.com\/devicexx\/espconn-esp32\">Espconn based on lwip on esp32<\/a><\/p>\n<h3>Hardware<\/h3>\n<p><a href=\"https:\/\/www.adafruit.com\/product\/3384\">Espressif ESP32 WROVER KIT<\/a>, Adafruit<br \/>\n<a href=\"https:\/\/wiki.wemos.cc\/products:lolin32:lolin32\">LOLIN32 &#8211; A wifi&#038;bluetooth board based ESP-32<\/a><br \/>\n<a href=\"https:\/\/wiki.wemos.cc\/products:d32:d32_pro\">D32 Pro<\/a><\/p>\n<h3>FreeRTOS<\/h3>\n<ul>\n<li>FreeRTOS 8.2.0 Custom ESP32<\/li>\n<li>FreeRTOS 9.0.0 Latest Release<\/li>\n<\/ul>\n<p><a href=\"http:\/\/www.freertos.org\/a00109.html\">Configuration<\/a><br \/>\n<a href=\"http:\/\/www.freertos.org\/a00110.html\">Customisation<\/a>7<br \/>\nFreeRTOS is customised using a configuration file called FreeRTOSConfig.h. Every FreeRTOS application must have a FreeRTOSConfig.h header file in its pre-processor include path. FreeRTOSConfig.h tailors the RTOS kernel to the application being built. It is therefore specific to the application, not the RTOS, and should be located in an application directory, not in one of the RTOS kernel source code directories. <\/p>\n<p><a href=\"http:\/\/www.lucadentella.it\/en\/2016\/12\/22\/esp32-4-flash-bootloader-e-freertos\/\">ESP32 (4) \u2013 Flash, bootloader and FreeRTOS<\/a><\/p>\n<p><a href=\"http:\/\/www.freertos.org\/a00127.html\"><code>vTaskDelay<\/code><\/a><\/p>\n<h4>Naming Conventions<\/h4>\n<p><a href=\"http:\/\/www.freertos.org\/FreeRTOS-Coding-Standard-and-Style-Guide.html\">Coding Standard and Style Guide<\/a><\/p>\n<p>Variables:<\/p>\n<ul>\n<li>Variables of type <strong><code>uint32_t<\/code><\/strong> are prefixed <strong><code>ul<\/code><\/strong>, where the <strong><code>'u'<\/code><\/strong> denotes <strong><code>'unsigned'<\/code><\/strong> and the <strong><code>'l<\/code>&#8216;<\/strong> denotes <strong><code>'long'<\/code><\/strong>.<\/li>\n<li>Variables of type <strong><code>uint16_t<\/code><\/strong> are prefixed <strong><code>us<\/code><\/strong>, where the <strong><code>'u'<\/code><\/strong> denotes <strong><code>'unsigned'<\/code><\/strong> and the <strong><code>'s'<\/code><\/strong> denotes <strong><code>'short'<\/code><\/strong>.<\/li>\n<li>Variables of type <strong><code>uint8_t<\/code><\/strong> are prefixed <strong><code>uc<\/code><\/strong>, where the <strong><code>'u'<\/code><\/strong> denotes <strong><code>'unsigned'<\/code><\/strong> and the <strong><code>'c'<\/code><\/strong> denotes <strong><code>'char'<\/code><\/strong>.<\/li>\n<li>Variables of non stdint types are prefixed <strong><code>x<\/code><\/strong>. Examples include <strong><code>BaseType_t<\/code><\/strong> and <strong><code>TickType_t<\/code><\/strong>, which are portable layer defined typedefs for the natural or most efficient type for the architecture and the type used to hold the RTOS tick count respectively.<\/li>\n<li>Unsigned variables of non stdint types have an additional prefix <strong><code>u<\/code><\/strong>. For example variables of type <strong><code>UBaseType_t<\/code><\/strong> (<strong><code>unsigned BaseType_t<\/code><\/strong>) are prefixed <strong><code>ux<\/code><\/strong>.<\/li>\n<li>Variables of type <strong><code>size_t<\/code><\/strong> are also prefixed <strong><code>x<\/code><\/strong>.<\/li>\n<li>Enumerated variables are prefixed <strong><code>e<\/code><\/strong><\/li>\n<li>Pointers have an additional prefixed <strong><code>p<\/code><\/strong>, for example a pointer to a <strong><code>uint16_t<\/code><\/strong> will have prefix <strong><code>pus<\/code><\/strong>.<\/li>\n<li>In line with MISRA guides, unqualified standard char types are only permitted to hold ASCII characters and are prefixed <strong><code>c<\/code><\/strong>.<\/li>\n<li>In line with MISRA guides, variables of type char * are only permitted to hold pointers to ASCII strings and are prefixed <strong><code>pc<\/code><\/strong>. <\/li>\n<\/ul>\n<p>Functions<\/p>\n<ul>\n<li>Same as variables.<\/li>\n<li>File scope static (private) functions are prefixed with <strong><code>prv<\/code><\/strong>. <\/li>\n<li>API functions are prefixed with their <em>return type<\/em>, as per the convention defined for variables, with the addition of the prefix <strong><code>v<\/code><\/strong> for <strong><code>void<\/code><\/strong>. <\/li>\n<li>API function names start with the name of the file in which they are defined. For example <strong><code>vTaskDelete()<\/code><\/strong> is defined in <strong><code>tasks.c<\/code><\/strong>, and has a <strong><code>void<\/code><\/strong> return type. <\/li>\n<\/ul>\n<h4>RTOS Task Notifications<\/h4>\n<p><a href=\"https:\/\/esp32.com\/viewtopic.php?f=13&#038;t=988\">untested functions in freertos<\/a><br \/>\n<a href=\"https:\/\/www.esp32.com\/viewtopic.php?f=13&#038;t=2313\">ESP32: Untested FreeRTOS function &#8220;ulTaskNotifyTake&#8221;<\/a><br \/>\n=> Don&#8217;t use Task Notifications, use<\/p>\n<ul>\n<li>Queue (for mailbox)<\/li>\n<li>Counting Semaphore<\/li>\n<li>EventGroups (for bitmask based flag events)<\/li>\n<\/ul>\n<pre class=\"brush: cpp; title: ; notranslate\" title=\"\">\r\nxTaskNotify()\r\nxTaskNotifyWait()\r\nresp.\r\n\r\nxTaskNotifyGive()\r\nulTaskNotifyTake() \r\n<\/pre>\n<h3>Ethernet<\/h3>\n<p><a href=\"https:\/\/www.tindie.com\/products\/microwavemont\/esp32-monster-board-ether-can-oled-all-in-one\/\">ESP32 Monster board, Ether, CAN, OLED all in one <\/a><br \/>\n<a href=\"https:\/\/hackaday.io\/project\/21321-esp32-monster-board\/log\/58539-details-about-board\">>ESP32 Monster board, Pinout &#038; schematic<\/a><br \/>\n<a href=\"https:\/\/www.tindie.com\/products\/microwavemont\/grande-esp32-monster-board\/\">GRANDE ESP32 Monster board<\/a><br \/>\n<a href=\"https:\/\/github.com\/kodera2t\/ESP32_OLED_LAN8720_sample\">kodera2t\/ESP32_OLED_LAN8720_sample<\/a><br \/>\n<a href=\"http:\/\/hackaday.com\/2017\/04\/18\/enabling-ethernet-on-the-esp32\/\">Enabling Ethernet On The ESP32<\/a><br \/>\n<a href=\"https:\/\/sautter.com\/blog\/ethernet-on-esp32-using-lan8720\/\">Ethernet on ESP32 using LAN8720<\/a><br \/>\n<a href=\"http:\/\/www.waveshare.com\/product\/modules\/communication\/ethernet.htm\">WaveShare Ethernet<\/a><br \/>\n<a href=\"http:\/\/www.waveshare.com\/wiki\/LAN8720_ETH_Board\">WaveShare Wiki &#8211; LAN8720 ETH Board<\/a><br \/>\n<a href=\"http:\/\/www.waveshare.com\/wiki\/DP83848_Ethernet_Board\">WaveShare Wiki &#8211; DP83848 Ethernet Board<\/a><br \/>\n<a href=\"https:\/\/www.heise.de\/make\/meldung\/ESP32-EVB-Development-Board-mit-WLAN-und-Ethernet-3625888.html\">ESP32-EVB: Development-Board mit WLAN und Ethernet<\/a><br \/>\n<a href=\"https:\/\/www.olimex.com\/Products\/IoT\/ESP32-EVB\/open-source-hardware\">Olimex ESP32-EVB<\/a><br \/>\n<a href=\"https:\/\/github.com\/russss\/esp32-ethernet\">An ESP32 board with ethernet support (LAN8720A)<\/a><br \/>\n<a href=\"https:\/\/www.bountysource.com\/issues\/42461310-add-lan8720-phy-support\">espressif\/esp-idf \u00bb Add LAN8720 phy support<\/a><br \/>\n<a href=\"https:\/\/www.esp32.com\/viewtopic.php?t=1149&#038;start=10\">[info] ESP32-EVB board for IoT with Ethernet 100Mb interface..<\/a><\/p>\n<h3>ROM<\/h3>\n<p><a href=\"https:\/\/gist.github.com\/igrr\/92f6115dd0986b3a82a46d2ba729b519\">These are the steps to build newlib used in ESP32 ROM and ESP-IDF <\/a><br \/>\n<a href=\"https:\/\/esp32.com\/viewtopic.php?f=2&#038;t=876\">ESP32 ROM update<\/a><\/p>\n<h3>MMU<\/h3>\n<p><a href=\"https:\/\/esp32.com\/viewtopic.php?f=12&#038;t=338\">Help in understanding the address mapping<\/a><\/p>\n<h3>Bluetooth<\/h3>\n<p><a href=\"https:\/\/en.wikipedia.org\/wiki\/Bluetooth_stack\">Wikipedia: Bluetooth stack<\/a><br \/>\n<a href=\"https:\/\/source.android.com\/devices\/bluetooth\">Android Bluetooth<\/a><br \/>\n<a href=\"https:\/\/stackoverflow.com\/questions\/20407326\/bluez-vs-bluedroid-bluetooth-stack\">BlueZ vs Bluedroid bluetooth stack<\/a><br \/>\n<a href=\"https:\/\/medium.com\/@zpcat\/bluedroid-stack-in-android-564c58b451f4\">Bluedroid stack in android<\/a><\/p>\n<h4>Bluetooth classic Example<\/h4>\n<p><a href=\"https:\/\/www.esp32.com\/viewtopic.php?f=13&#038;t=1209\">Bluetooth classic<\/a><\/p>\n<p>It&#8217;s definitely not hardware. They&#8217;re using a Riviera Waves\/CEVA IP core for at least the controller if not the modem side, per their and CEVA&#8217;s press releases. That&#8217;s full function to 4.1\/4.2 as a dual mode device. The problem, apparently, is that they&#8217;re implementing the full embedded profile design which means it kind-of skips the HCI being propagated through a channel and you don&#8217;t have a raw HCI edge, only an API. Definitely annoying since they claim full support on the chip. That equates to all the hooks to drive that hardware fully, which is very definitely NOT the case.<\/p>\n<ul>\n<li>Riviera Waves\/CEVA IP<\/li>\n<li>&#8230;<\/li>\n<\/ul>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\nBLE   = Bluetooth Low Energy\r\nBT    = Bluetooth Classic\r\nBTDM  = Bluetooth Dual Mode (BTDM)\r\n\r\nBTE   = Bluetooth Embedded System\r\nBTA   = Bluetooth Application Layer\r\n\r\n<\/pre>\n<h4>VHCI<\/h4>\n<pre class=\"brush: cpp; title: ; notranslate\" title=\"\">\r\n\/** @brief esp_vhci_host_callback\r\n *  used for vhci call host function to notify what host need to do\r\n *\/\r\ntypedef struct esp_vhci_host_callback {\r\n    void (*notify_host_send_available)(void);               \/*!&lt; callback used to notify that the host can send packet to controller *\/\r\n    int (*notify_host_recv)(uint8_t *data, uint16_t len);   \/*!&lt; callback used to notify that the controller has a packet to send to the host*\/\r\n} esp_vhci_host_callback_t;\r\n\r\n\r\n\/** @brief esp_vhci_host_register_callback\r\n * register the vhci referece callback, the call back\r\n * struct defined by vhci_host_callback structure.\r\n * @param callback esp_vhci_host_callback type variable\r\n *\/\r\nvoid esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback);\r\n<\/pre>\n<h4>I2S<\/h4>\n<p><a href=\"http:\/\/iot-bits.com\/interfacing-an-audio-codec-with-esp32\/\">Interfacing an audio codec with ESP32<\/a>, June 7, 2017<br \/>\n<a href=\"http:\/\/iot-bits.com\/freertos-event-groups-quick-reference-notes\/\">FreeRTOS Event Groups \u2013 quick reference notes<\/a><\/p>\n<h4>Kolban<\/h4>\n<p><a href=\"https:\/\/www.youtube.com\/channel\/UChKn_BlaVrMrhEquPNI6HuQ\">Channel: t Technical Tutorials<\/a><br \/>\n<a href=\"https:\/\/www.youtube.com\/watch?v=2_vlF_02VXk\">ESP32 Technical Tutorials: BLE and C++<\/a><br \/>\n<a href=\"https:\/\/github.com\/nkolban\/esp32-snippets\/tree\/master\/cpp_utils\">github.com\/nkolban\/esp32-snippets\/cpp_utils<\/a><\/p>\n<h4>Bluedroid<\/h3>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\ntypedef struct {\r\n    void (* btc_call)(btc_msg_t *msg);\r\n    void (* btc_cb)(btc_msg_t *msg);\r\n} btc_func_t;\r\n\r\nstatic btc_func_t profile_tab&#x5B;BTC_PID_NUM] = {\r\n    &#x5B;BTC_PID_MAIN_INIT] = {btc_main_call_handler,       NULL                    },\r\n    &#x5B;BTC_PID_DEV]       = {btc_dev_call_handler,        NULL                    },\r\n    &#x5B;...]\r\n};\r\n\r\nesp-idf\/components\/bt\/include\/bt.h                         esp_vhci_host_send_packet(uint8_t *data, uint16_t len)\r\nesp-idf\/components\/bt\/bluedroid\/hci\/hci_hal_h4.c           transmit_data(type, uint8_t *data, uint16_t length)\r\nesp-idf\/components\/bt\/bluedroid\/hci\/hci_hal_h4.c           interface\r\nesp-idf\/components\/bt\/bluedroid\/hci\/hci_hal_h4.c           hci_hal_h4_get_interface()\r\nesp-idf\/components\/bt\/bluedroid\/hci\/hci_layer.c            hci_layer_get_interface()\r\nesp-idf\/components\/bt\/bluedroid\/main\/bte_main.c            bte_main_boot_entry(bluedroid_init_done_cb_t cb)\r\nesp-idf\/components\/bt\/bluedroid\/btc\/core\/btc_main.c        btc_init_bluetooth(void)\r\nesp-idf\/components\/bt\/bluedroid\/btc\/core\/btc_main.c        btc_main_call_handler(btc_msg_t *msg)\r\nesp-idf\/components\/bt\/bluedroid\/btc\/core\/btc_task.c        profile_tab&#x5B;BTC_PID_NUM]\r\n\r\nesp-idf\/components\/bt\/bluedroid\/btc\/core\/btc_task.c        profile_tab&#x5B;msg.pid].btc_call(&amp;msg);\r\nesp-idf\/components\/bt\/bluedroid\/btc\/core\/btc_task.c        btc_task(void *arg)\r\nesp-idf\/components\/bt\/bluedroid\/btc\/core\/btc_task.c        btc_init(void)\r\nesp-idf\/components\/bt\/bluedroid\/api\/esp_bt_main.c          esp_bluedroid_init(void)\r\nesp-idf\/examples\/bluetooth\/gatt_server\/main\/gatts_demo.c   app_main()\r\nesp-idf\/components\/esp32\/cpu_start.c                       main_task(void* args)\r\n<\/pre>\n<h3>Future vs. Thread<\/h3>\n<p>Context of future_t object correct in ESP32?<\/p>\n<p><a href=\"http:\/\/preshing.com\/20120612\/an-introduction-to-lock-free-programming\/\">An Introduction to Lock-Free Programming<\/a><br \/>\n<a href=\"http:\/\/preshing.com\/20120913\/acquire-and-release-semantics\/\">Acquire and Release Semantics<\/a><br \/>\n<a href=\"https:\/\/stackoverflow.com\/questions\/14456276\/semaphores-and-threadpools-in-java\">Semaphores and Threadpools in Java<\/a><br \/>\n<a href=\"https:\/\/blog.codecentric.de\/2011\/10\/tasks-parallel-ausfuhren-mit-java-future\/\">Tasks parallel ausf\u00fchren mit Java Future<\/a><br \/>\n<a href=\"http:\/\/winterbe.com\/posts\/2015\/04\/07\/java8-concurrency-tutorial-thread-executor-examples\/\">Java 8 Concurrency Tutorial: Threads and Executors<\/a><br \/>\n<a href=\"http:\/\/docs.oracle.com\/javase\/6\/docs\/api\/java\/util\/concurrent\/Future.html\">Interface Future<V><\/a><br \/>\nA <code>Future<\/code> represents the result of an asynchronous computation. Methods are provided to check if the computation is complete, to wait for its completion, and to retrieve the result of the computation. The result can only be retrieved using method <code>get<\/code> when the computation has completed, blocking if necessary until it is ready. <\/p>\n<p><a href=\"https:\/\/docs.racket-lang.org\/reference\/futures.html\">Futures<\/a><br \/>\nThe <code>future<\/code> access to parallelism as supported by the hardware and operating system. In contrast to <code>thread<\/code>, which provides concurrency for arbitrary computations without parallelism, <code>future<\/code> provides parallelism for limited computations. A <code>future<\/code> executes its work in parallel (assuming that support for parallelism is available) until it detects an attempt to perform an operation that is too complex for the system to run safely in parallel. Similarly, work in a <code>future<\/code> is suspended if it depends in some way on the current continuation, such as raising an exception.<\/p>\n<p>\u201cSafe\u201d parallel execution of a <code>future<\/code> means that all operations provided by the system must be able to enforce contracts and produce results as documented. \u201cSafe\u201d does not preclude concurrent access to mutable data that is visible in the program. For example, a computation in a <code>future<\/code> might use set! to modify a shared variable, in which case concurrent assignment to the variable can be visible in other <code>futures<\/code> and <code>threads<\/code>. Furthermore, guarantees about the visibility of effects and ordering are determined by the operating system and hardware\u2014which rarely support, for example, the guarantee of sequential consistency that is provided for <code>thread<\/code>-based concurrency. At the same time, operations that seem obviously safe may have a complex enough implementation internally that they cannot run in parallel.<\/p>\n<h3>Arduino<\/h3>\n<p><a href=\"https:\/\/learn.sparkfun.com\/tutorials\/esp32-thing-hookup-guide\">Sparkfun ESP32 Thing Hookup Guide<\/a><br \/>\n<a href=\"https:\/\/github.com\/plerup\/makeEspArduino\">makeEspArduino &#8211; A makefile for ESP8266 and ESP32 Arduino projects<\/a><\/p>\n<h3>Deep-Sleep<\/h3>\n<p><a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/api-reference\/system\/deep_sleep.html\">System API \u00bb Deep Sleep<\/a><br \/>\n<a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/api-guides\/deep-sleep-stub.html\">API Guides \u00bb Deep Sleep Wake Stubs<\/a><\/p>\n<h3>YouTube<\/h3>\n<p><a href=\"https:\/\/www.youtube.com\/watch?v=rP9p0MzxSos&#038;list=PLxJ8_KSR8bp5-F4HVG4QOm4Kt6wQhzsjU\">pcbreflux&#8217;s ESP32 Playlist<\/a><\/p>\n<h4>Andreas Spiess<\/h4>\n<p><a href=\"https:\/\/www.youtube.com\/watch?v=r75MrWIVIw4\">#149 ESP32 Deep Sleep, RTC Memory, &#8220;Secret&#8221; LoLin Pins<\/a><\/p>\n<h3>Tutorials<\/h3>\n<p><a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/\">ESP-IDF Programming Guide<\/a><br \/>\n<a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/get-started\/index.html\">Get Started<\/a> (ESP IDF, official, latest)<\/p>\n<h3>Debug<\/h3>\n<p><a href=\"http:\/\/openocd.org\/doc-release\/README\">OpenOCD README<\/a><br \/>\n<a href=\"http:\/\/wiki.jackslab.org\/ESP32_JTAG\">ESP32 JTAG<\/a><\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\n# Check if user is in group &quot;plugdev&quot;\r\n$ groups\r\nandreas adm dialout cdrom sudo dip video plugdev lpadmin sambashare wireshark\r\n\r\n# Copy OpenOCD rules to udev and restart\r\n$ sudo cp .\/share\/openocd\/contrib\/99-openocd.rules \/etc\/udev\/rules.d\r\n$ sudo service udev restart\r\n\r\n$ bin\/openocd -s share\/openocd\/scripts -f interface\/ftdi\/tumpa.cfg -f board\/esp-wroom-32.cfg\r\nOpen On-Chip Debugger 0.10.0-dev-ga859564 (2017-07-24-16:16)\r\nLicensed under GNU GPL v2\r\nFor bug reports, read\r\n\thttp:\/\/openocd.org\/doc\/doxygen\/bugs.html\r\nnone separate\r\nadapter speed: 20000 kHz\r\nforce hard breakpoints\r\nInfo : ftdi: if you experience problems at higher adapter clocks, try the command &quot;ftdi_tdo_sample_edge falling&quot;\r\nInfo : clock speed 20000 kHz\r\nInfo : JTAG tap: esp32.cpu0 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nInfo : JTAG tap: esp32.cpu1 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nInfo : esp32: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).\r\nInfo : esp32: Core was reset (pwrstat=0x5F, after clear 0x0F).\r\n&#x5B;...]\r\n&gt;&gt;&gt; start GDB &lt;&lt;&lt;\r\n&#x5B;...]\r\nInfo : accepting 'gdb' connection on tcp\/3333\r\nInfo : Target halted. PRO_CPU: PC=0x400D12B4 (active)    APP_CPU: PC=0x00000000 \r\nesp32: target state: halted\r\nInfo : Use core0 of target 'esp32'\r\nInfo : Target halted. PRO_CPU: PC=0x40091D07 (active)    APP_CPU: PC=0x400D12B4 \r\nInfo : Auto-detected flash size 4096 KB\r\nInfo : Using flash size 4096 KB\r\nInfo : Set current thread to 0x00000000, old= 0x00000000\r\nInfo : JTAG tap: esp32.cpu0 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nInfo : JTAG tap: esp32.cpu1 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nInfo : esp32: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).\r\nInfo : esp32: Core was reset (pwrstat=0x5F, after clear 0x0F).\r\nInfo : Target halted. PRO_CPU: PC=0x5000004B (active)    APP_CPU: PC=0x00000000 \r\nesp32: target state: halted\r\nInfo : esp32: Core was reset (pwrstat=0x1F, after clear 0x0F).\r\nInfo : Target halted. PRO_CPU: PC=0x40000400 (active)    APP_CPU: PC=0x40000400 \r\nesp32: target state: halted\r\nInfo : Target halted. PRO_CPU: PC=0x400D171F (active)    APP_CPU: PC=0x400850A4 \r\n\r\n$ xtensa-esp32-elf-gdb -x gdbinit build\/blink.elf \r\nGNU gdb (crosstool-NG crosstool-ng-1.22.0-61-gab8375a) 7.10\r\nCopyright (C) 2015 Free Software Foundation, Inc.\r\nLicense GPLv3+: GNU GPL version 3 or later &lt;http:\/\/gnu.org\/licenses\/gpl.html&gt;\r\nThis is free software: you are free to change and redistribute it.\r\nThere is NO WARRANTY, to the extent permitted by law.  Type &quot;show copying&quot;\r\nand &quot;show warranty&quot; for details.\r\nThis GDB was configured as &quot;--host=x86_64-build_pc-linux-gnu --target=xtensa-esp32-elf&quot;.\r\nType &quot;show configuration&quot; for configuration details.\r\nFor bug reporting instructions, please see:\r\n&lt;http:\/\/www.gnu.org\/software\/gdb\/bugs\/&gt;.\r\nFind the GDB manual and other documentation resources online at:\r\n&lt;http:\/\/www.gnu.org\/software\/gdb\/documentation\/&gt;.\r\nFor help, type &quot;help&quot;.\r\nType &quot;apropos word&quot; to search for commands related to &quot;word&quot;...\r\nReading symbols from build\/blink.elf...done.\r\n0x400d12b4 in esp_vApplicationIdleHook () at \/home\/andreas\/esp32\/esp-idf\/components\/esp32\/.\/freertos_hooks.c:52\r\n52\t        asm(&quot;waiti 0&quot;);\r\nJTAG tap: esp32.cpu0 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nJTAG tap: esp32.cpu1 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nesp32: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).\r\nesp32: Core was reset (pwrstat=0x5F, after clear 0x0F).\r\nTarget halted. PRO_CPU: PC=0x5000004B (active)    APP_CPU: PC=0x00000000 \r\nesp32: target state: halted\r\nesp32: Core was reset (pwrstat=0x1F, after clear 0x0F).\r\nTarget halted. PRO_CPU: PC=0x40000400 (active)    APP_CPU: PC=0x40000400 \r\nesp32: target state: halted\r\nHardware assisted breakpoint 1 at 0x400d171f: file \/home\/andreas\/esp32\/apps\/blink\/main\/.\/blink.c, line 43.\r\n0x0:\t0x00000000\r\nTarget halted. PRO_CPU: PC=0x400D171F (active)    APP_CPU: PC=0x400850A4 \r\n&#x5B;New Thread 1073413728]\r\n&#x5B;New Thread 1073413372]\r\n&#x5B;New Thread 1073433120]\r\n&#x5B;New Thread 1073431992]\r\n&#x5B;New Thread 1073410212]\r\n&#x5B;New Thread 1073408748]\r\n&#x5B;New Thread 1073411340]\r\n&#x5B;Switching to Thread 1073411776]\r\n\r\nTemporary breakpoint 1, app_main () at \/home\/andreas\/esp32\/apps\/blink\/main\/.\/blink.c:43\r\n43\t    xTaskCreate(&amp;blink_task, &quot;blink_task&quot;, configMINIMAL_STACK_SIZE, NULL, 5, NULL);\r\n(gdb) \r\n\r\n(gdb) b blink.c:33\r\nBreakpoint 2 at 0x400d16fe: file \/home\/andreas\/esp32\/apps\/blink\/main\/.\/blink.c, line 33.\r\n(gdb) continue\r\nContinuing.\r\nTarget halted. PRO_CPU: PC=0x400D16FE (active)    APP_CPU: PC=0x400850A4 \r\n&#x5B;New Thread 1073434248]\r\n&#x5B;Switching to Thread 1073434248]\r\n\r\nBreakpoint 2, blink_task (pvParameter=0x0) at \/home\/andreas\/esp32\/apps\/blink\/main\/.\/blink.c:33\r\n33\t        gpio_set_level(BLINK_GPIO, 0);\r\n(gdb) n\r\nTarget halted. PRO_CPU: PC=0x400D1700 (active)    APP_CPU: PC=0x400850A4 \r\nTarget halted. PRO_CPU: PC=0x400D1703 (active)    APP_CPU: PC=0x400850A4 \r\nTarget halted. PRO_CPU: PC=0x400DCA58 (active)    APP_CPU: PC=0x400850A4 \r\nTarget halted. PRO_CPU: PC=0x400D1706 (active)    APP_CPU: PC=0x400850A4 \r\n34\t        vTaskDelay(1000 \/ portTICK_PERIOD_MS);\r\n(gdb) n\r\nTarget halted. PRO_CPU: PC=0x400D1709 (active)    APP_CPU: PC=0x400850A4 \r\nTarget halted. PRO_CPU: PC=0x40084458 (active)    APP_CPU: PC=0x400850A4 \r\nTarget halted. PRO_CPU: PC=0x400D170C (active)    APP_CPU: PC=0x400D12B4 \r\n36\t        gpio_set_level(BLINK_GPIO, 1);\r\n(gdb) n\r\nTarget halted. PRO_CPU: PC=0x400D170E (active)    APP_CPU: PC=0x400D12B4 \r\nTarget halted. PRO_CPU: PC=0x400D1710 (active)    APP_CPU: PC=0x400D12B4 \r\nTarget halted. PRO_CPU: PC=0x400DCA58 (active)    APP_CPU: PC=0x400D12B4 \r\nTarget halted. PRO_CPU: PC=0x400D1713 (active)    APP_CPU: PC=0x400D12B4 \r\n37\t        vTaskDelay(1000 \/ portTICK_PERIOD_MS);\r\n(gdb) n\r\nTarget halted. PRO_CPU: PC=0x400D1716 (active)    APP_CPU: PC=0x400D12B4 \r\nTarget halted. PRO_CPU: PC=0x40084458 (active)    APP_CPU: PC=0x400D12B4 \r\nTarget halted. PRO_CPU: PC=0x400D1719 (active)    APP_CPU: PC=0x400D12B4 \r\nTarget halted. PRO_CPU: PC=0x400D16FE (active)    APP_CPU: PC=0x400D12B4\r\n\r\n(gdb) layout asm\r\n   6\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\nB+ &lt;0x400d16fe &lt;blink_task+18&gt;              movi.n a11, 0\r\n   &lt;0x400d1700 &lt;blink_task+20&gt;              movi   a10, 5 \r\n   &lt;0x400d1703 &lt;blink_task+23&gt;              call8  0x400dca58 &lt;gpio_set_level&gt;\r\n   &lt;0x400d1706 &lt;blink_task+26&gt;              movi   a10, 100\r\n   &lt;0x400d1709 &lt;blink_task+29&gt;              call8  0x40084458 &lt;vTaskDelay&gt;\r\n   &lt;0x400d170c &lt;blink_task+32&gt;              movi.n a11, 1\r\n   &lt;0x400d170e &lt;blink_task+34&gt;              movi.n a10, 5\r\n   &lt;0x400d1710 &lt;blink_task+36&gt;              call8  0x400dca58 &lt;gpio_set_level&gt;\r\n   &lt;0x400d1713 &lt;blink_task+39&gt;              movi   a10, 100\r\n   &lt;0x400d1716 &lt;blink_task+42&gt;              call8  0x40084458 &lt;vTaskDelay&gt;\r\n   &lt;0x400d1719 &lt;blink_task+45&gt;              j      0x400d16fe &lt;blink_task+18&gt;\r\n\r\n(gdb) tui enable\r\n(gdb) tui disable\r\n\r\n<\/pre>\n<pre class=\"brush: plain; title: Errors; notranslate\" title=\"Errors\">\r\n$ bin\/openocd -s share\/openocd\/scripts -f interface\/ftdi\/tumpa.cfg -f board\/esp-wroom-32.cfg\r\nOpen On-Chip Debugger 0.10.0-dev-ga859564 (2017-07-24-16:16)\r\nLicensed under GNU GPL v2\r\nFor bug reports, read\r\n\thttp:\/\/openocd.org\/doc\/doxygen\/bugs.html\r\nnone separate\r\nadapter speed: 20000 kHz\r\nforce hard breakpoints\r\nInfo : ftdi: if you experience problems at higher adapter clocks, try the command &quot;ftdi_tdo_sample_edge falling&quot;\r\nInfo : clock speed 20000 kHz\r\nError: JTAG scan chain interrogation failed: all ones\r\nError: Check JTAG interface, timings, target power, etc.\r\nError: Trying to use configured scan chain anyway...\r\nError: esp32.cpu0: IR capture error; saw 0x1f not 0x01\r\nWarn : Bypassing JTAG setup events due to errors\r\nInfo : esp32: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).\r\nInfo : esp32: Core was reset (pwrstat=0x5F, after clear 0x0F).\r\nInfo : esp32: Debug controller was reset (pwrstat=0xE5, after clear 0x5F).\r\n\r\n$ bin\/openocd -s share\/openocd\/scripts -f interface\/ftdi\/tumpa.cfg -f board\/esp-wroom-32.cfg\r\nOpen On-Chip Debugger 0.10.0-dev-ga859564 (2017-07-24-16:16)\r\nLicensed under GNU GPL v2\r\nFor bug reports, read\r\n\thttp:\/\/openocd.org\/doc\/doxygen\/bugs.html\r\nnone separate\r\nadapter speed: 20000 kHz\r\nforce hard breakpoints\r\nInfo : ftdi: if you experience problems at higher adapter clocks, try the command &quot;ftdi_tdo_sample_edge falling&quot;\r\nInfo : clock speed 20000 kHz\r\nError: JTAG scan chain interrogation failed: all ones\r\nError: Check JTAG interface, timings, target power, etc.\r\nError: Trying to use configured scan chain anyway...\r\nError: esp32.cpu0: IR capture error; saw 0x1f not 0x01\r\nWarn : Bypassing JTAG setup events due to errors\r\nInfo : esp32: Debug controller was reset (pwrstat=0xFF, after clear 0xFF).\r\nInfo : esp32: Core was reset (pwrstat=0xFF, after clear 0xFF).\r\nError: cpu0: esp32_fetch_all_regs (line 163): DSR (FFFFFFFF) indicates target still busy!\r\nError: cpu0: esp32_fetch_all_regs (line 163): DSR (FFFFFFFF) indicates DIR instruction generated an exception!\r\nError: cpu0: esp32_fetch_all_regs (line 163): DSR (FFFFFFFF) indicates DIR instruction generated an overrun!\r\nError: cpu0: esp32_fetch_all_regs (line 190): DSR (FFFFFFFF) indicates target still busy!\r\nError: cpu0: esp32_fetch_all_regs (line 190): DSR (FFFFFFFF) indicates DIR instruction generated an exception!\r\nError: cpu0: esp32_fetch_all_regs (line 190): DSR (FFFFFFFF) indicates DIR instruction generated an overrun!\r\nError: Exception reading pc!\r\nInfo : Target halted. PRO_CPU: PC=0x00000000             APP_CPU: PC=0x00000000 (active)\r\nError: cpu0: xtensa_write_memory (line 696): DSR (FFFFFFFF) indicates target still busy!\r\nError: cpu0: xtensa_write_memory (line 696): DSR (FFFFFFFF) indicates DIR instruction generated an exception!\r\nError: cpu0: xtensa_write_memory (line 696): DSR (FFFFFFFF) indicates DIR instruction generated an overrun!\r\nWarn : esp32: Failed writing 4 bytes at address 0x3FF5F064, data - a1, 3a, d8, 50, a1, 3a, d8, 50\r\n\r\n$ xtensa-esp32-elf-gdb -x gdbinit build\/app-template.elf \r\nGNU gdb (crosstool-NG crosstool-ng-1.22.0-61-gab8375a) 7.10\r\nCopyright (C) 2015 Free Software Foundation, Inc.\r\nLicense GPLv3+: GNU GPL version 3 or later &lt;http:\/\/gnu.org\/licenses\/gpl.html&gt;\r\nThis is free software: you are free to change and redistribute it.\r\nThere is NO WARRANTY, to the extent permitted by law.  Type &quot;show copying&quot;\r\nand &quot;show warranty&quot; for details.\r\nThis GDB was configured as &quot;--host=x86_64-build_pc-linux-gnu --target=xtensa-esp32-elf&quot;.\r\nType &quot;show configuration&quot; for configuration details.\r\nFor bug reporting instructions, please see:\r\n&lt;http:\/\/www.gnu.org\/software\/gdb\/bugs\/&gt;.\r\nFind the GDB manual and other documentation resources online at:\r\n&lt;http:\/\/www.gnu.org\/software\/gdb\/documentation\/&gt;.\r\nFor help, type &quot;help&quot;.\r\nType &quot;apropos word&quot; to search for commands related to &quot;word&quot;...\r\nReading symbols from build\/app-template.elf...done.\r\n0x400da440 in ieee80211_send_mgmt ()\r\nJTAG tap: esp32.cpu0 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nJTAG tap: esp32.cpu1 tap\/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)\r\nesp32: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).\r\nesp32: Core was reset (pwrstat=0x5F, after clear 0x0F).\r\nTarget halted. PRO_CPU: PC=0x5000004B (active)    APP_CPU: PC=0x00000000 \r\nesp32: target state: halted\r\nesp32: Core was reset (pwrstat=0x1F, after clear 0x0F).\r\nTarget halted. PRO_CPU: PC=0x40000400 (active)    APP_CPU: PC=0x40000400 \r\nesp32: target state: halted\r\nHardware assisted breakpoint 1 at 0x400f49f8: file \/home\/andreas\/esp32\/apps\/myapp\/main\/.\/main.c, line 15.\r\n0x0:\t0x00000000\r\n<\/pre>\n<p><a href=\"https:\/\/esp-idf.readthedocs.io\/en\/v1.0\/openocd.html\">Debugging &#8211; OpenOCD setup for ESP32<\/a><br \/>\n<a href=\"http:\/\/www.diygadget.com\/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html\">TIAO USB Multi-Protocol Adapter (JTAG, SPI, I2C, Serial)<\/a> (FT2232H)<br \/>\n<a href=\"http:\/\/www.tiaowiki.com\/w\/TIAO_USB_Multi_Protocol_Adapter_User%27s_Manual\">TIAO USB Multi Protocol Adapter User&#8217;s Manual<\/a><br \/>\n<a href=\"http:\/\/www.tincantools.com\/JTAG\/Flyswatter2.html\">Flyswatter2<\/a> (FT2232H)<br \/>\n<a href=\"http:\/\/www.ftdichip.com\/Products\/ICs\/FT2232H.html\">FT2232H &#8211; Hi-Speed Dual USB UART\/FIFO IC<\/a><\/p>\n<p><a href=\"http:\/\/blog.podkalicki.com\/esp32-building-the-toolchain-for-linux-ubuntu\/\">ESP32 \u2013 building the toolchain for Linux (Ubuntu)<\/a><\/p>\n<p><a href=\"https:\/\/hackaday.com\/2017\/05\/03\/hands-on-hot-new-wemos-esp-32-breakout\/\">Hands-On the Hot New WeMos ESP-32 Breakout<\/a><br \/>\n<a href=\"https:\/\/www.mikrocontroller.net\/articles\/ESP32\">mikrocontroller.net\/articles\/ESP32<\/a><br \/>\n<a href=\"http:\/\/blog.podkalicki.com\/esp32-building-the-toolchain-for-linux-ubuntu\/\">ESP32 \u2013 building the toolchain for Linux (Ubuntu)<\/a><br \/>\n<a href=\"http:\/\/www.lucadentella.it\/en\/2017\/01\/30\/esp32-8-connessione-tcp\/\">ESP32 (8) \u2013 tcp connection<\/a><br \/>\n<a href=\"https:\/\/www.sparkfun.com\/news\/2017\">Enginursday: First Impressions of the ESP32<\/a><br \/>\n<a href=\"https:\/\/exploreembedded.com\/wiki\/\">exploreembedded.com &#8211; Wiki<\/a><br \/>\n<a href=\"https:\/\/exploreembedded.com\/wiki\/Hello_World_with_ESP32_Explained\">exploreembedded.com &#8211; Hello World with ESP32 Explained<\/a><br \/>\n<a href=\"http:\/\/fab.cba.mit.edu\/classes\/4.140\/doc\/tutorials\/ESP32\/index.html\">ESP32 &#8211; FIRST STEPS<\/a><\/p>\n<h3>Closed-Source Libraries<\/h3>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\n.\/esp-idf\/components\/bt\/lib\/libbtdm_app.a\r\n.\/esp-idf\/components\/newlib\/lib\/libm.a\r\n.\/esp-idf\/components\/newlib\/lib\/libc_nano.a\r\n.\/esp-idf\/components\/newlib\/lib\/libg.a\r\n.\/esp-idf\/components\/newlib\/lib\/libc.a\r\n.\/esp-idf\/components\/esp32\/libhal.a\r\n.\/esp-idf\/components\/esp32\/lib\/libnet80211.a\r\n.\/esp-idf\/components\/esp32\/lib\/libwpa2.a\r\n.\/esp-idf\/components\/esp32\/lib\/libwps.a\r\n.\/esp-idf\/components\/esp32\/lib\/libwpa.a\r\n.\/esp-idf\/components\/esp32\/lib\/libsmartconfig.a\r\n.\/esp-idf\/components\/esp32\/lib\/libphy.a\r\n.\/esp-idf\/components\/esp32\/lib\/libcore.a\r\n.\/esp-idf\/components\/esp32\/lib\/libcoexist.a\r\n.\/esp-idf\/components\/esp32\/lib\/librtc.a\r\n.\/esp-idf\/components\/esp32\/lib\/libpp.a\r\n<\/pre>\n<h3>Books<\/h3>\n<p>SparkFun ESP32 Thing Development Workshop, von Agus Kurniawan<br \/>\nKolban&#8217;s book on ESP32, von Neil Kolban<\/p>\n<h3>Dual-Core and Tasks<\/h3>\n<p><a href=\"http:\/\/exploreembedded.com\/wiki\/Task_Switching\">Task Switching<\/a><br \/>\nFreeRTOS is currently configured to use one of the timers built into the CPU core (<strong><code>CCOMPARE0<\/code><\/strong>).<\/p>\n<p><a href=\"https:\/\/www.esp32.com\/viewtopic.php?t=1293\">ESP-IDF, multicore &#038; freeRTOS confusion<\/a><\/p>\n<p><a href=\"https:\/\/esp32.com\/viewtopic.php?f=2&#038;t=1336\">Getting started with FreeRtos<\/a><br \/>\nAlso don&#8217;t call <strong><code>vTaskStartScheduler()<\/code><\/strong>, this function is called before <strong><code>app_main<\/code><\/strong> starts. In fact, <strong><code>app_main<\/code><\/strong> runs within a FreeRTOS task already.<\/p>\n<p><a href=\"https:\/\/www.esp32.com\/viewtopic.php?f=2&#038;t=764\">Use of dual core<\/a><br \/>\nThe second core is normally enabled. You can disable it using the sdkconfig file, which you would normally &#8216;edit&#8217; by running &#8216;make menuconfig&#8217;. If you start up a task using the FreeRTOS xTaskCreate function, FreeRTOS will automatically run the task on any of the two CPUs, whichever one is free. You can also &#8216;pin&#8217; a task to one single CPU by using xTaskCreatePinnedToCore.<\/p>\n<pre class=\"brush: cpp; title: ; notranslate\" title=\"\">\r\nxTaskCreatePinnedToCore()\r\nxTaskCreate()\r\n\r\nArguments:\r\nTaskFunction_t         pxTaskCode,\r\nconst char * const     pcName,\r\nconst uint32_t         usStackDepth,\r\nvoid * const           pvParameters,\r\nUBaseType_t            uxPriority,\r\nTaskHandle_t * const   pxCreatedTask,\r\nconst BaseType_t       xCoreID = { 0, 1, tskNO_AFFINITY }\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/fatfs\/test\/test_fatfs_common.c; notranslate\" title=\"esp-idf\/components\/fatfs\/test\/test_fatfs_common.c\">\r\ntypedef struct {\r\n    const char* filename;\r\n    bool write;\r\n    size_t word_count;\r\n    int seed;\r\n    SemaphoreHandle_t done;\r\n    int result;\r\n} read_write_test_arg_t;\r\n\r\n#define READ_WRITE_TEST_ARG_INIT(name, seed_) \\\r\n        { \\\r\n            .filename = name, \\\r\n            .seed = seed_, \\\r\n            .word_count = 8192, \\\r\n            .write = true, \\\r\n            .done = xSemaphoreCreateBinary() \\\r\n        }\r\n\r\nstatic void read_write_task(void* param)\r\n{\r\n    read_write_test_arg_t* args = (read_write_test_arg_t*) param;\r\n\r\n    &#x5B;...]\r\n}\r\n\r\n&#x5B;...]\r\n\r\nvoid test_fatfs_concurrent(const char* filename_prefix)\r\n{\r\n    char names&#x5B;4]&#x5B;64];\r\n    for (size_t i = 0; i &lt; 4; ++i) {\r\n        snprintf(names&#x5B;i], sizeof(names&#x5B;i]), &quot;%s%d&quot;, filename_prefix, i + 1);\r\n        unlink(names&#x5B;i]);\r\n    }\r\n\r\n    read_write_test_arg_t args1 = READ_WRITE_TEST_ARG_INIT(names&#x5B;0], 1);\r\n    read_write_test_arg_t args2 = READ_WRITE_TEST_ARG_INIT(names&#x5B;1], 2);\r\n\r\n    printf(&quot;writing f1 and f2\\n&quot;);\r\n\r\n    xTaskCreatePinnedToCore(&amp;read_write_task, &quot;rw1&quot;, 2048, &amp;args1, 3, NULL, 0);\r\n    xTaskCreatePinnedToCore(&amp;read_write_task, &quot;rw2&quot;, 2048, &amp;args2, 3, NULL, 1);\r\n\r\n    &#x5B;...]\r\n}\r\n&#x5B;...]\r\n<\/pre>\n<h3>techtutorialsx<\/h3>\n<p><a href=\"https:\/\/techtutorialsx.com\/2017\/05\/09\/esp32-get-task-execution-core\/\">ESP32: Get Task execution core<\/a><br \/>\n<a href=\"https:\/\/techtutorialsx.com\/2017\/05\/09\/esp32-running-code-on-a-specific-core\/\">ESP32: Running code on a specific core<\/a><br \/>\n<a href=\"https:\/\/techtutorialsx.com\/2017\/05\/16\/esp32-dual-core-execution-speedup\/\">ESP32: Dual core execution speedup<\/a><\/p>\n<h3>Mutex + Semaphores<\/h3>\n<p><a href=\"https:\/\/github.com\/espressif\/esp-idf\/issues\/498\">components\/driver\/rmt: portENTER_CRITICAL called from ISR context<\/a><br \/>\n<a href=\"https:\/\/github.com\/espressif\/esp-idf\/blob\/master\/components\/freertos\/include\/freertos\/portmacro.h#L177\"> esp-idf\/components\/freertos\/include\/freertos\/portmacro.h<\/a><\/p>\n<pre class=\"brush: cpp; title: ; notranslate\" title=\"\">\r\nportENTER_CRITICAL\r\n       vs\r\ntaskENTER_CRITICAL\r\n       vs\r\nvTaskEnterCritical\r\n\r\n=================================\r\n\r\nportMUX_TYPE adc_spinlock = portMUX_INITIALIZER_UNLOCKED;\r\n\r\nportENTER_CRITICAL(&amp;adc_spinlock);\r\n&#x5B;...]\r\nportEXIT_CRITICAL(&amp;adc_spinlock);\r\n\r\n=====\r\n vs.\r\n=====\r\n\r\nvoid vTaskEnterCritical( portMUX_TYPE *mux )\r\nvoid vTaskExitCritical( portMUX_TYPE *mux )\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/freertos\/include\/freertos\/portmacro.h; notranslate\" title=\"esp-idf\/components\/freertos\/include\/freertos\/portmacro.h\">\r\n\/*\r\nModifications to portENTER_CRITICAL:\r\n\r\nThe original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by \r\ndisabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because\r\ninterrupts are disabled, ISRs can't corrupt data structures either.\r\n\r\nFor multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop\r\nthe tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding\r\na spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will\r\nspinlock in the portENTER_CRITICAL code until the first CPU is done.\r\n\r\nFor ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same\r\nCPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the\r\ndata. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks\r\ndo not disable the interrupts (because they already are).\r\n\r\nThis all assumes that interrupts are either entirely disabled or enabled. Interrupr priority levels\r\nwill break this scheme.\r\n\r\nRemark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vTaskEnterCritical, meaning\r\nthat either function can be called both from ISR as well as task context. This is not standard FreeRTOS \r\nbehaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.\r\n*\/\r\n\r\n&#x5B;...]\r\nvoid vTaskEnterCritical( portMUX_TYPE *mux );\r\nvoid vTaskExitCritical( portMUX_TYPE *mux );\r\n&#x5B;...]\r\n\r\n#define portENTER_CRITICAL(mux)        vTaskEnterCritical(mux)\r\n#define portEXIT_CRITICAL(mux)         vTaskExitCritical(mux)\r\n#define portENTER_CRITICAL_ISR(mux)    vTaskEnterCritical(mux)\r\n#define portEXIT_CRITICAL_ISR(mux)     vTaskExitCritical(mux)\r\n<\/pre>\n<pre class=\"brush: cpp; title: ; notranslate\" title=\"\">\r\n\/**\r\n * task. h\r\n *\r\n * Macro to mark the start of a critical code region.  Preemptive context\r\n * switches cannot occur when in a critical region.\r\n *\r\n * NOTE: This may alter the stack (depending on the portable implementation)\r\n * so must be used with care!\r\n *\r\n * \\defgroup taskENTER_CRITICAL taskENTER_CRITICAL\r\n * \\ingroup SchedulerControl\r\n *\/\r\n#define taskENTER_CRITICAL(mux)         portENTER_CRITICAL(mux)\r\n#define taskENTER_CRITICAL_ISR(mux)     portENTER_CRITICAL_ISR(mux)\r\n\r\n\/**\r\n * task. h\r\n *\r\n * Macro to mark the end of a critical code region.  Preemptive context\r\n * switches cannot occur when in a critical region.\r\n *\r\n * NOTE: This may alter the stack (depending on the portable implementation)\r\n * so must be used with care!\r\n *\r\n * \\defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL\r\n * \\ingroup SchedulerControl\r\n *\/\r\n#define taskEXIT_CRITICAL(mux)          portEXIT_CRITICAL(mux)\r\n#define taskEXIT_CRITICAL_ISR(mux)      portEXIT_CRITICAL_ISR(mux)\r\n<\/pre>\n<h3>FAQ<\/h3>\n<h4>Linker fails: libraries not found<\/h4>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\n$ xtensa-esp32-elf-gcc test.c\r\n\/opt\/xtensa-esp32-elf\/bin\/..\/lib\/gcc\/xtensa-esp32-elf\/5.2.0\/..\/..\/..\/..\/xtensa-esp32-elf\/bin\/ld: cannot find crt1-sim.o: No such file or directory\r\n\/opt\/xtensa-esp32-elf\/bin\/..\/lib\/gcc\/xtensa-esp32-elf\/5.2.0\/..\/..\/..\/..\/xtensa-esp32-elf\/bin\/ld: cannot find _vectors.o: No such file or directory\r\n\/opt\/xtensa-esp32-elf\/bin\/..\/lib\/gcc\/xtensa-esp32-elf\/5.2.0\/..\/..\/..\/..\/xtensa-esp32-elf\/bin\/ld: cannot find -lsim\r\n\/opt\/xtensa-esp32-elf\/bin\/..\/lib\/gcc\/xtensa-esp32-elf\/5.2.0\/..\/..\/..\/..\/xtensa-esp32-elf\/bin\/ld: cannot find -lhandlers-sim\r\n\/opt\/xtensa-esp32-elf\/bin\/..\/lib\/gcc\/xtensa-esp32-elf\/5.2.0\/..\/..\/..\/..\/xtensa-esp32-elf\/bin\/ld: cannot find -lhal\r\ncollect2: error: ld returned 1 exit status\r\n<\/pre>\n<h3>Program Structure<\/h3>\n<p><a href=\"https:\/\/github.com\/espressif\/esp-idf\/blob\/master\/docs\/api-guides\/general-notes.rst\">General Notes About ESP-IDF Programming<\/a>,<br \/>\n<a href=\"https:\/\/github.com\/espressif\/esp-idf\/blob\/master\/docs\/api-guides\/build-system.rst\">Build System<\/a>, Makefile structure<\/p>\n<ul>\n<li>PRO CPU = cpu0<\/li>\n<li>APP CPU = cpu1<\/li>\n<\/ul>\n<pre class=\"brush: plain; collapse: true; light: false; title: Code Snippets; toolbar: true; notranslate\" title=\"Code Snippets\">\r\n$ grep -r start_cpu0\r\n&#x5B;...]\r\ncomponents\/bootloader\/src\/main\/bootloader_start.c:void IRAM_ATTR call_start_cpu0()\r\ncomponents\/bootloader\/src\/main\/esp32.bootloader.ld:ENTRY(call_start_cpu0);\r\ncomponents\/esp32\/ld\/esp32.common.ld:ENTRY(call_start_cpu0);\r\ncomponents\/esp32\/cpu_start.c:void start_cpu0(void) __attribute__((weak, alias(&quot;start_cpu0_default&quot;)));\r\ncomponents\/esp32\/cpu_start.c:void start_cpu0_default(void) IRAM_ATTR;\r\ncomponents\/esp32\/cpu_start.c:void IRAM_ATTR call_start_cpu0()\r\ncomponents\/esp32\/cpu_start.c:    start_cpu0();\r\ncomponents\/esp32\/cpu_start.c:void start_cpu0_default(void)\r\ncomponents\/spi_flash\/cache_utils.c:        \/\/ called from the 2nd stage bootloader or from user_start_cpu0, i.e. from\r\nmake\/project.mk:\t-u call_user_start_cpu0\t\\\r\n&#x5B;...]\r\n\r\n$ grep -r component.mk\r\n&#x5B;...]\r\nmake\/project.mk:# This Makefile is included directly from the user project Makefile in order to call the component.mk\r\nmake\/project.mk:# A component is buildable if it has a component.mk makefile in it\r\nmake\/project.mk:COMPONENT_PATHS_BUILDABLE := $(foreach cp,$(COMPONENT_PATHS),$(if $(wildcard $(cp)\/component.mk),$(cp)))\r\nmake\/project.mk:# stored in COMPONENT_LINKER_DEPS, built via component.mk files' COMPONENT_ADD_LINKER_DEPS variable\r\nmake\/project.mk:+$(MAKE) -C $(BUILD_DIR_BASE)\/$(2) -f $(IDF_PATH)\/make\/component_wrapper.mk COMPONENT_MAKEFILE=$(1)\/component.mk COMPONENT_NAME=$(2)\r\nmake\/project.mk:$(BUILD_DIR_BASE)\/$(2)\/component_project_vars.mk: $(1)\/component.mk $(COMMON_MAKEFILES) $(SDKCONFIG_MAKEFILE) | $(BUILD_DIR_BASE)\/$(2)\r\n&#x5B;...]\r\n\r\ncomponents\/bootloader\/src\/main\/esp32.bootloader.ld (Second stage bootloader)\r\n==================================================\r\nENTRY(call_start_cpu0);\r\n\r\ncomponents\/bootloader\/src\/main\/bootloader_start.c (Second stage bootloader)\r\n=================================================\r\nvoid IRAM_ATTR call_start_cpu0()\r\nvoid bootloader_main()\r\nstatic void set_cache_and_start_app(&#x5B;...])\r\n    entry_t entry = ((entry_t) entry_addr);\r\n    (*entry)();\r\n\r\ncomponents\/esp32\/cpu_start.c (Application startup)\r\n============================\r\nvoid start_cpu0(void) __attribute__((weak, alias(&quot;start_cpu0_default&quot;)));\r\nvoid start_cpu0_default(void) IRAM_ATTR;\r\n\r\nvoid IRAM_ATTR call_start_cpu0()\r\nvoid start_cpu0(void) =&gt; default!\r\nvoid start_cpu0_default(void)\r\n    xTaskCreatePinnedToCore(&amp;main_task, &quot;main&quot;,\r\n            ESP_TASK_MAIN_STACK, NULL,\r\n            ESP_TASK_MAIN_PRIO, NULL, 0);\r\nstatic void main_task(void* args)\r\napp_main();\r\n\r\n$ grep -r call_start_cpu1 .\r\n&#x5B;...]\r\n.\/components\/esp32\/cpu_start.c:static void IRAM_ATTR call_start_cpu1();\r\n.\/components\/esp32\/cpu_start.c:    ESP_EARLY_LOGI(TAG, &quot;Starting app cpu, entry point is %p&quot;, call_start_cpu1);\r\n.\/components\/esp32\/cpu_start.c:    ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);\r\n.\/components\/esp32\/cpu_start.c:void IRAM_ATTR call_start_cpu1()\r\n\r\n$ grep -r ets_set_appcpu_boot_addr .\r\n.\/components\/esptool_py\/esptool\/flasher_stub\/rom_32.ld:PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );\r\n.\/components\/bootloader\/src\/main\/bootloader_start.c:    ets_set_appcpu_boot_addr(0); \r\n.\/components\/esp32\/ld\/esp32.rom.ld:PROVIDE ( ets_set_appcpu_boot_addr = 0x4000689c );\r\n.\/components\/esp32\/cpu_start.c:    ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);\r\n.\/components\/esp32\/cpu_start.c:    ets_set_appcpu_boot_addr(0);\r\n.\/components\/esp32\/include\/rom\/ets_sys.h:void ets_set_appcpu_boot_addr(uint32_t start);\r\n\r\n<\/pre>\n<h3>FreeRTOS SMP-aware<\/h3>\n<p><a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/api-reference\/system\/intr_alloc.html\">Interrupt allocation<\/a><br \/>\n<a href=\"https:\/\/github.com\/espressif\/esp-idf\/blob\/master\/components\/freertos\/readme_smp.txt\">esp-idf\/components\/freertos\/readme_smp.txt<\/a><\/p>\n<p>Interrupts: <\/p>\n<ul>\n<li>Enabling and disabling interrupts will only affect the current core.<\/li>\n<li>Use a mux, queue or semaphore to protect your structures instead.<\/li>\n<\/ul>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\n$ grep -r xTaskCreatePinnedToCore\r\n&#x5B;...]\r\n.\/components\/freertos\/include\/freertos\/task.h:    BaseType_t xTaskCreatePinnedToCore(\tTaskFunction_t pxTaskCode,\r\n.\/components\/freertos\/include\/freertos\/task.h:#define xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask ) xTaskCreatePinnedToCore( ( pvTaskCode ), ( pcName ), ( usStackDepth ), ( pvParameters ), ( uxPriority ), ( pxCreatedTask ), tskNO_AFFINITY )\r\n&#x5B;...]\r\ncomponents\/freertos\/tasks.c:\tBaseType_t xTaskCreatePinnedToCore(\tTaskFunction_t pxTaskCode,\r\ncomponents\/freertos\/tasks.c:\t\t\txReturn = xTaskCreatePinnedToCore( prvIdleTask, &quot;IDLE&quot;, tskIDLE_STACK_SIZE, ( void * ) NULL, ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), &amp;xIdleTaskHandle&#x5B;i], i ); \/*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. *\/\r\n&#x5B;...]\r\n<\/pre>\n<h3>Interrupts, Interrupt Handlers, User Exception Handlers<\/h3>\n<h4>Documentation \/ Guide<\/h4>\n<p><a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/api-reference\/system\/intr_alloc.html\">Interrupt allocation<\/a><br \/>\n<a href=\"http:\/\/esp-idf.readthedocs.io\/en\/latest\/api-guides\/hlinterrupts.html\">High-Level Interrupts<\/a><br \/>\n<a href=\"https:\/\/www.esp32.com\/viewtopic.php?t=422\">External Interrupt Latency<\/a><\/p>\n<h4>Code<\/h4>\n<p><a href=\"https:\/\/github.com\/espressif\/esp-idf\/blob\/master\/docs\/api-reference\/system\/intr_alloc.rst\">esp-idf\/docs\/api-reference\/system\/intr_alloc.rst<\/a><br \/>\n<a href=\"https:\/\/github.com\/espressif\/esp-idf\/blob\/master\/docs\/api-guides\/hlinterrupts.rst\">esp-idf\/docs\/api-guides\/hlinterrupts.rst<\/a><\/p>\n<pre class=\"brush: cpp; title: UART Interrupt Chain; notranslate\" title=\"UART Interrupt Chain\">\r\nesp-idf\/components\/driver\/uart.c\r\nuart_driver_install()\r\n  p_uart_obj&#x5B;uart_num]-&gt;xQueueUart  = xQueueCreate(queue_size, sizeof(uart_event_t));\r\n  p_uart_obj&#x5B;uart_num]-&gt;rx_ring_buf = xRingbufferCreate(rx_buffer_size, RINGBUF_TYPE_BYTEBUF);\r\n  p_uart_obj&#x5B;uart_num]-&gt;tx_ring_buf = xRingbufferCreate(tx_buffer_size, RINGBUF_TYPE_NOSPLIT);\r\n\r\nesp-idf\/components\/driver\/uart.c\r\nuart_rx_intr_handler_default()\r\n  p_uart-&gt;tx_head = (uart_tx_data_t*) xRingbufferReceiveFromISR(p_uart-&gt;tx_ring_buf, &amp;size);\r\n\r\n  \/\/Get the buffer from the FIFO\r\n  rx_fifo_len = uart_reg-&gt;status.rxfifo_cnt;\r\n  p_uart-&gt;rx_stash_len = rx_fifo_len;\r\n  \/\/We have to read out all data in RX FIFO to clear the interrupt signal\r\n  while(buf_idx &lt; rx_fifo_len) {\r\n      p_uart-&gt;rx_data_buf&#x5B;buf_idx++] = uart_reg-&gt;fifo.rw_byte;\r\n  }\r\n  xRingbufferSendFromISR(p_uart-&gt;rx_ring_buf, p_uart-&gt;rx_data_buf, p_uart-&gt;rx_stash_len, &amp;HPTaskAwoken)\r\n\r\nesp-idf\/components\/soc\/esp32\/include\/soc\/uart_reg.h\r\n  #define UART_RXFIFO_RD_BYTE  0x000000FF (register itself)\r\n\r\nesp-idf\/components\/soc\/esp32\/include\/soc\/uart_struct.h\r\n  typedef struct uart_dev_t (register as struct)\r\n\r\n\r\nesp-idf\/components\/freertos\/xtensa_vectors.S     _Level2Vector\r\nesp-idf\/components\/freertos\/xtensa_vectors.S     dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK\r\nesp-idf\/components\/freertos\/xtensa_intr_asm.S    _xt_interrupt_table\r\nesp-idf\/components\/freertos\/xtensa_intr.c        extern _xt_interrupt_table\r\nesp-idf\/components\/freertos\/xtensa_intr.c        xt_set_interrupt_handler()\r\nesp-idf\/components\/esp32\/intr_alloc.c            esp_intr_alloc_intrstatus()\r\nesp-idf\/components\/esp32\/intr_alloc.c            esp_intr_alloc()\r\nesp-idf\/components\/driver\/uart.c                 uart_isr_register()\r\nesp-idf\/components\/driver\/uart.c                 uart_driver_install()\r\n<\/pre>\n<pre class=\"brush: cpp; title: Timer Interrupt Chain; notranslate\" title=\"Timer Interrupt Chain\">\r\n\r\nesp-idf\/components\/esp32\/ld\/esp32.peripherals.ld\r\n  PROVIDE ( TIMERG0 = 0x3ff5F000 );\r\n  PROVIDE ( TIMERG1 = 0x3ff60000 );\r\n\r\nesp-idf\/components\/soc\/esp32\/include\/soc\/timer_group_struct.h\r\n  extern timg_dev_t TIMERG0;\r\n  extern timg_dev_t TIMERG1;\r\n\r\nesp-idf\/components\/esp32\/intr_alloc.c     esp_intr_alloc_intrstatus()\r\n                                            xt_set_interrupt_handler()\r\n                                            intr_matrix_set()\r\n                                            ESP_INTR_ENABLE(intr);\r\nesp-idf\/components\/driver\/timer.c         timer_isr_register()\r\nesp-idf\/examples\/peripherals\/timer_group\/main\/timer_group_example_main.c\r\n\r\n<\/pre>\n<pre class=\"brush: plain; title: CCOMPARE0 \/ TIMER0; notranslate\" title=\"CCOMPARE0 \/ TIMER0\">\r\n$ grep -r CCOMPARE0 .\r\nesp-idf\/components\/esp32\/include\/xtensa\/hal.h:                #define XTHAL_MAX_TIMERS            4   \/* max number of timers (CCOMPARE0..CCOMPARE3) *\/\r\nesp-idf\/components\/esp32\/include\/xtensa\/config\/core-isa.h:    #define XCHAL_TIMER0_INTERRUPT      6   \/* CCOMPARE0 *\/\r\n\r\n$ grep -r XCHAL_TIMER0_INTERRUPT .\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) &lt;= XCHAL_EXCM_LEVEL\r\n\r\n$ grep -r _xt_tick_divisor_init .\r\nesp-idf\/components\/freertos\/portasm.S:                        * Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).\r\nesp-idf\/components\/freertos\/portasm.S:                        _frxt_timer_int:\r\nesp-idf\/components\/freertos\/portasm.S:                        _frxt_tick_timer_init:\r\nesp-idf\/components\/freertos\/port.c:                          _xt_tick_divisor_init();\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:  extern void     _xt_tick_divisor_init(void);\r\nesp-idf\/components\/freertos\/xtensa_init.c:                    void _xt_tick_divisor_init(void)\r\n\r\n$ grep -r _frxt_timer_int .\r\nesp-idf\/components\/freertos\/portasm.S:                        _frxt_timer_int:\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_rtos.h:   #define XT_RTOS_TIMER_INT   _frxt_timer_int\r\n\r\n$ grep -r XT_RTOS_TIMER_INT .\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 call0   XT_RTOS_TIMER_INT\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 call4   XT_RTOS_TIMER_INT\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_rtos.h:   #define XT_RTOS_TIMER_INT   _frxt_timer_int\r\nesp-idf\/components\/freertos\/xtensa_init.c:                    #ifdef XT_RTOS_TIMER_INT\r\n\r\n$ grep -r XT_TIMER_INTEN .\r\nesp-idf\/components\/freertos\/portasm.S:                        movi    a2, XT_TIMER_INTEN\r\nesp-idf\/components\/freertos\/portasm.S:                        movi    a6, XT_TIMER_INTEN\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 movi    a3, XT_TIMER_INTEN      \/* a3 = timer interrupt bit *\/\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:  #define XT_TIMER_INTEN          (1 &lt;&lt; XT_TIMER_INTNUM)\r\n\r\n$ grep -r XT_TIMER_INTNUM .\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:  #define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:  #define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:  #define XT_TIMER_INTEN          (1 &lt;&lt; XT_TIMER_INTNUM)\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h:  #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED\r\n\r\n$ grep -r xt_set_interrupt_handler .\r\nesp-idf\/components\/freertos\/xtensa_intr.c:                    xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)\r\nesp-idf\/components\/freertos\/include\/freertos\/xtensa_api.h:    extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg))\r\nesp-idf\/components\/esp32\/include\/esp_intr.h:                  xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg))\r\n\r\n$ grep -r xt_handler_table_entry\r\nesp-idf\/components\/freertos\/xtensa_intr.c:                    typedef struct xt_handler_table_entry {\r\nesp-idf\/components\/freertos\/xtensa_intr.c:                    extern xt_handler_table_entry _xt_interrupt_table&#x5B;XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];\r\nesp-idf\/components\/esp32\/intr_alloc.c:                        typedef struct xt_handler_table_entry\r\nesp-idf\/components\/esp32\/intr_alloc.c:                        extern xt_handler_table_entry _xt_interrupt_table&#x5B;XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];\r\n\r\n$ grep -r _xt_interrupt_table\r\nesp-idf\/components\/freertos\/xtensa_intr.c:                    extern xt_handler_table_entry _xt_interrupt_table&#x5B;XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 movi    a4, _xt_interrupt_table\r\nesp-idf\/components\/freertos\/xtensa_intr_asm.S:               _xt_interrupt_table:\r\nesp-idf\/components\/esp32\/intr_alloc.c:                        extern xt_handler_table_entry _xt_interrupt_table&#x5B;XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];\r\n\r\n]$ grep -r dispatch_c_isr .\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 Macro dispatch_c_isr - dispatch interrupts to user ISRs.\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 .macro  dispatch_c_isr    level  mask\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK\r\n\r\n$ grep -r InterruptVector .\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 .section    .Level2InterruptVector.text, &quot;ax&quot;\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 .section    .Level3InterruptVector.text, &quot;ax&quot;\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 .section    .Level4InterruptVector.text, &quot;ax&quot;\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 .section    .Level5InterruptVector.text, &quot;ax&quot;\r\nesp-idf\/components\/freertos\/xtensa_vectors.S:                 .section    .Level6InterruptVector.text, &quot;ax&quot;\r\nesp-idf\/components\/esp32\/ld\/esp32.common.ld:                  KEEP(*(.Level2InterruptVector.text));\r\nesp-idf\/components\/esp32\/ld\/esp32.common.ld:                  KEEP(*(.Level3InterruptVector.text));\r\nesp-idf\/components\/esp32\/ld\/esp32.common.ld:                  KEEP(*(.Level4InterruptVector.text));\r\nesp-idf\/components\/esp32\/ld\/esp32.common.ld:                  KEEP(*(.Level5InterruptVector.text));\r\n\r\n$ grep -rE &quot;Vector =|Exception =|Interrupt =&quot; .\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _DebugExceptionVector = 0x40000280 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _DoubleExceptionVector = 0x400003c0 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _KernelExceptionVector = 0x40000300 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _GeneralException = 0x40000e14 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _ResetVector = 0x40000400 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _UserExceptionVector = 0x40000340 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _NMIExceptionVector = 0x400002c0 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level2FromVector = 0x40000954 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level3FromVector = 0x40000a28 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level4FromVector = 0x40000af8 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level5FromVector = 0x40000c68 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level2Vector = 0x40000180 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level3Vector = 0x400001c0 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level4Vector = 0x40000200 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _Level5Vector = 0x40000240 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _LevelOneInterrupt = 0x40000835 );\r\nesp-idf\/components\/esp32\/ld\/esp32.rom.ld:                     PROVIDE ( _SyscallException = 0x400007cf );\r\n\r\n<\/pre>\n<pre class=\"brush: plain; title: esp-idf\/components\/soc\/esp32\/include\/soc\/soc.h; notranslate\" title=\"esp-idf\/components\/soc\/esp32\/include\/soc\/soc.h\">\r\n\/\/CPU0 Interrupt number reserved, not touch this.\r\n#define ETS_WMAC_INUM                           0\r\n#define ETS_BT_HOST_INUM                        1\r\n#define ETS_WBB_INUM                            4\r\n#define ETS_TG0_T1_INUM                         10 \/**&lt; use edge interrupt*\/\r\n#define ETS_FRC1_INUM                           22\r\n#define ETS_T1_WDT_INUM                         24\r\n#define ETS_CACHEERR_INUM                       25\r\n#define ETS_DPORT_INUM                          31\r\n\r\n\/\/CPU0 Interrupt number used in ROM, should be cancelled in SDK\r\n#define ETS_SLC_INUM                            1\r\n#define ETS_UART0_INUM                          5\r\n#define ETS_UART1_INUM                          5\r\n\/\/Other interrupt number should be managed by the user\r\n\r\n\/\/Invalid interrupt for number interrupt matrix\r\n#define ETS_INVALID_INUM                        6\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/freertos\/xtensa_intr.c; notranslate\" title=\"esp-idf\/components\/freertos\/xtensa_intr.c\">\r\n\r\n\/* Handler table is in xtensa_intr_asm.S *\/\r\n\r\ntypedef struct xt_handler_table_entry {\r\n    void * handler;\r\n    void * arg;\r\n} xt_handler_table_entry;\r\n\r\nextern xt_handler_table_entry _xt_interrupt_table&#x5B;XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];\r\n\r\n\/*\r\n  This function registers a handler for the specified interrupt. The &quot;arg&quot;\r\n  parameter specifies the argument to be passed to the handler when it is\r\n  invoked. The function returns the address of the previous handler.\r\n  On error, it returns 0.\r\n*\/\r\nxt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)\r\n{\r\n    xt_handler_table_entry * entry;\r\n    xt_handler               old;\r\n\r\n    if( n &lt; 0 || n &gt;= XCHAL_NUM_INTERRUPTS )\r\n        return 0;       \/* invalid interrupt number *\/\r\n    if( Xthal_intlevel&#x5B;n] &gt; XCHAL_EXCM_LEVEL )\r\n        return 0;       \/* priority level too high to safely handle in C *\/\r\n\r\n    \/* Convert exception number to _xt_exception_table name *\/\r\n    n = n * portNUM_PROCESSORS + xPortGetCoreID();\r\n\r\n    entry = _xt_interrupt_table + n;\r\n    old   = entry-&gt;handler;\r\n\r\n    if (f) {\r\n        entry-&gt;handler = f;\r\n        entry-&gt;arg     = arg;\r\n    }\r\n    else {\r\n        entry-&gt;handler = &amp;xt_unhandled_interrupt;\r\n        entry-&gt;arg     = (void*)n;\r\n    }\r\n\r\n    return ((old == &amp;xt_unhandled_interrupt) ? 0 : old);\r\n}\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/freertos\/xtensa_intr_asm.S; notranslate\" title=\"esp-idf\/components\/freertos\/xtensa_intr_asm.S\">\r\n\/******************************************************************************\r\n  Xtensa interrupt handling data and assembly routines.\r\n  Also see xtensa_intr.c and xtensa_vectors.S.\r\n******************************************************************************\/\r\n\r\n&#x5B;...]\r\n\r\n\/*\r\n-------------------------------------------------------------------------------\r\n  Table of C-callable interrupt handlers for each interrupt. Note that not all\r\n  slots can be filled, because interrupts at level &gt; EXCM_LEVEL will not be\r\n  dispatched to a C handler by default.\r\n\r\n  Stored as:\r\n  int 0 cpu 0\r\n  int 0 cpu 1\r\n  ...\r\n  int 0 cpu n\r\n  int 1 cpu 0\r\n  int 1 cpu 1\r\n  etc\r\n-------------------------------------------------------------------------------\r\n*\/\r\n_xt_interrupt_table:\r\n    .set    i, 0\r\n    .rept   XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS\r\n    .word   xt_unhandled_interrupt      \/* handler address               *\/\r\n    .word   i                           \/* handler arg (default: intnum) *\/\r\n    .set    i, i+1\r\n    .endr\r\n\r\n\/*\r\n-------------------------------------------------------------------------------\r\n  Table of C-callable exception handlers for each exception. Note that not all\r\n  slots will be active, because some exceptions (e.g. coprocessor exceptions)\r\n  are always handled by the OS and cannot be hooked by user handlers.\r\n\r\n  Stored as:\r\n  exc 0 cpu 0\r\n  exc 0 cpu 1\r\n  ...\r\n  exc 0 cpu n\r\n  exc 1 cpu 0\r\n  exc 1 cpu 1\r\n  etc\r\n-------------------------------------------------------------------------------\r\n*\/\r\n_xt_exception_table:\r\n    .rept   XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS\r\n    .word   xt_unhandled_exception    \/* handler address *\/\r\n    .endr\r\n\r\n\r\n\/*\r\n-------------------------------------------------------------------------------\r\n  unsigned int xt_ints_on ( unsigned int mask )\r\n\r\n  Enables a set of interrupts. Does not simply set INTENABLE directly, but\r\n  computes it as a function of the current virtual priority if XT_USE_SWPRI is\r\n  enabled.\r\n  Can be called from interrupt handlers.\r\n-------------------------------------------------------------------------------\r\n*\/\r\nxt_ints_on:\r\n\r\n&#x5B;...]\r\n\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/freertos\/xtensa_vectors.S; notranslate\" title=\"esp-idf\/components\/freertos\/xtensa_vectors.S\">\r\n\/*******************************************************************************\r\n        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS\r\n\r\n  Xtensa low level exception and interrupt vectors and handlers for an RTOS.\r\n\r\n  Interrupt handlers and user exception handlers support interaction with\r\n  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and\r\n  after user's specific interrupt handlers. These macros are defined in\r\n  xtensa_&lt;rtos&gt;.h to call suitable functions in a specific RTOS.\r\n\r\n  Users can install application-specific interrupt handlers for low and\r\n  medium level interrupts, by calling xt_set_interrupt_handler(). These\r\n  handlers can be written in C, and must obey C calling convention. The\r\n  handler table is indexed by the interrupt number. Each handler may be\r\n  provided with an argument. \r\n\r\n  Note that the system timer interrupt is handled specially, and is\r\n  dispatched to the RTOS-specific handler. This timer cannot be hooked\r\n  by application code.\r\n\r\n  Optional hooks are also provided to install a handler per level at \r\n  run-time, made available by compiling this source file with \r\n  '-DXT_INTEXC_HOOKS' (useful for automated testing).\r\n\r\n!!  This file is a template that usually needs to be modified to handle       !!\r\n!!  application specific interrupts. Search USER_EDIT for helpful comments    !!\r\n!!  on where to insert handlers and how to write them.                        !!\r\n\r\n  Users can also install application-specific exception handlers in the\r\n  same way, by calling xt_set_exception_handler(). One handler slot is\r\n  provided for each exception type. Note that some exceptions are handled\r\n  by the porting layer itself, and cannot be taken over by application\r\n  code in this manner. These are the alloca, syscall, and coprocessor\r\n  exceptions.\r\n\r\n  The exception handlers can be written in C, and must follow C calling\r\n  convention. Each handler is passed a pointer to an exception frame as\r\n  its single argument. The exception frame is created on the stack, and\r\n  holds the saved context of the thread that took the exception. If the\r\n  handler returns, the context will be restored and the instruction that\r\n  caused the exception will be retried. If the handler makes any changes\r\n  to the saved state in the exception frame, the changes will be applied\r\n  when restoring the context.\r\n\r\n  Because Xtensa is a configurable architecture, this port supports all user\r\n  generated configurations (except restrictions stated in the release notes).\r\n  This is accomplished by conditional compilation using macros and functions\r\n  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.\r\n  Only the relevant parts of this file will be included in your RTOS build.\r\n  For example, this file provides interrupt vector templates for all types and\r\n  all priority levels, but only the ones in your configuration are built.\r\n\r\n  NOTES on the use of 'call0' for long jumps instead of 'j':\r\n   1. This file should be assembled with the -mlongcalls option to xt-xcc.\r\n   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to\r\n      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the\r\n      distance from the call to the destination. The linker then relaxes\r\n      it back to 'call0 dest' if it determines that dest is within range.\r\n      This allows more flexibility in locating code without the performance\r\n      overhead of the 'l32r' literal data load in cases where the destination\r\n      is in range of 'call0'. There is an additional benefit in that 'call0'\r\n      has a longer range than 'j' due to the target being word-aligned, so \r\n      the 'l32r' sequence is less likely needed.\r\n   3. The use of 'call0' with -mlongcalls requires that register a0 not be \r\n      live at the time of the call, which is always the case for a function \r\n      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.\r\n   4. This use of 'call0' is independent of the C function call ABI.\r\n\r\n*******************************************************************************\/\r\n\r\n&#x5B;...]\r\n\r\n\/*\r\n--------------------------------------------------------------------------------\r\n  Macro dispatch_c_isr - dispatch interrupts to user ISRs.\r\n  This will dispatch to user handlers (if any) that are registered in the\r\n  XTOS dispatch table (_xtos_interrupt_table). These handlers would have\r\n  been registered by calling _xtos_set_interrupt_handler(). There is one\r\n  exception - the timer interrupt used by the OS will not be dispatched\r\n  to a user handler - this must be handled by the caller of this macro.\r\n\r\n  Level triggered and software interrupts are automatically deasserted by\r\n  this code.\r\n\r\n  ASSUMPTIONS:\r\n    -- PS.INTLEVEL is set to &quot;level&quot; at entry\r\n    -- PS.EXCM = 0, C calling enabled\r\n\r\n  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.\r\n\r\n  NOTE: This macro will use registers a0 and a2-a6. The arguments are:\r\n    level -- interrupt level\r\n    mask  -- interrupt bitmask for this level\r\n--------------------------------------------------------------------------------\r\n*\/\r\n\r\n.macro  dispatch_c_isr    level  mask\r\n\r\n\/* Get mask of pending, enabled interrupts at this level into a2. *\/\r\n.L_xt_user_int_&amp;level&amp;:\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/freertos\/include\/freertos\/xtensa_rtos.h; notranslate\" title=\"esp-idf\/components\/freertos\/include\/freertos\/xtensa_rtos.h\">\r\n\/*\r\n        RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES\r\n                            (FreeRTOS Port)\r\n\r\nThis header is the primary glue between generic Xtensa RTOS support\r\nsources and a specific RTOS port for Xtensa.  It contains definitions\r\nand macros for use primarily by Xtensa assembly coded source files.\r\n\r\nMacros in this header map callouts from generic Xtensa files to specific\r\nRTOS functions. It may also be included in C source files.\r\n\r\nXtensa RTOS ports support all RTOS-compatible configurations of the Xtensa \r\narchitecture, using the Xtensa hardware abstraction layer (HAL) to deal \r\nwith configuration specifics.\r\n\r\nShould be included by all Xtensa generic and RTOS port-specific sources.\r\n*\/\r\n\r\n&#x5B;..]\r\n\r\n\/*\r\nInform RTOS of the occurrence of a tick timer interrupt.\r\nIf RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.\r\nMay be coded in or called from C or assembly, per ABI conventions.\r\nRTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).\r\n*\/\r\n#define XT_RTOS_TIMER_INT   _frxt_timer_int\r\n#define XT_TICK_PER_SEC     configTICK_RATE_HZ\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h; notranslate\" title=\"esp-idf\/components\/freertos\/include\/freertos\/xtensa_timer.h\">\r\n\/*\r\n        XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY\r\n\r\nThis header contains definitions and macros for use primarily by Xtensa\r\nRTOS assembly coded source files. It includes and uses the Xtensa hardware\r\nabstraction layer (HAL) to deal with config specifics. It may also be\r\nincluded in C source files.\r\n\r\nUser may edit to modify timer selection and to specify clock frequency and\r\ntick duration to match timer interrupt to the real-time tick duration.\r\n\r\nIf the RTOS has no timer interrupt, then there is no tick timer and the\r\nclock frequency is irrelevant, so all of these macros are left undefined\r\nand the Xtensa core configuration need not have a timer.\r\n*\/\r\n<\/pre>\n<pre class=\"brush: cpp; title: esp-idf\/components\/freertos\/portasm.S; notranslate\" title=\"esp-idf\/components\/freertos\/portasm.S\">\r\n\/*\r\n**********************************************************************************************************\r\n*                                           _frxt_timer_int\r\n*                                      void _frxt_timer_int(void)\r\n*\r\n* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.\r\n* Called every timer interrupt.\r\n* Manages the tick timer and calls xPortSysTickHandler() every tick.\r\n* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.\r\n*\r\n* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.\r\n*\r\n**********************************************************************************************************\r\n*\/\r\n&#x5B;...]\r\n_frxt_timer_int:\r\n&#x5B;...]\r\n    call0   xPortSysTickHandler\r\n&#x5B;...]\r\n\r\n\/*\r\n**********************************************************************************************************\r\n*                                           _frxt_tick_timer_init\r\n*                                      void _frxt_tick_timer_init(void)\r\n*\r\n* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).\r\n* Callable from C (obeys ABI conventions on entry).\r\n*\r\n**********************************************************************************************************\r\n*\/\r\n&#x5B;...]\r\n_frxt_tick_timer_init:\r\n&#x5B;...]\r\n    \/*\r\n    Enable the timer interrupt at the device level. Don't write directly\r\n    to the INTENABLE register because it may be virtualized.\r\n    *\/\r\n    movi    a2, XT_TIMER_INTEN\r\n    call0   xt_ints_on\r\n&#x5B;...]\r\n<\/pre>\n<pre class=\"brush: plain; title: esp-idf\/components\/freertos\/readme_xtensa.txt; notranslate\" title=\"esp-idf\/components\/freertos\/readme_xtensa.txt\">\r\n&#x5B;...]\r\n\r\nInterrupt and Exception Handling\r\n--------------------------------\r\n\r\nFreeRTOS provides a complete set of efficient exception and first-level\r\ninterrupt handlers installed at the appropriate exception and interrupt\r\nvector locations. The Xtensa architecture supports several different\r\nclasses of exceptions and interrupts. Being a configurable architecture,\r\nmany of these are optional, and the vector locations are determined by\r\nyour processor configuration. (Note that Diamond cores are pre-configured\r\nwith specific vector locations.) The handlers provided use conditional\r\ncompilation to adapt to your processor configuration and include only \r\nthe code that is needed.\r\n\r\nXtensa vector locations may reside almost anywhere, including in ROM.\r\nThe amount of code space available at each of these locations is\r\noften very small (e.g. due to following vectors). A small stub of\r\ncode installed at the vector jumps to the corresponding handler,\r\nusually in RAM. The exception and interrupt handlers are defined in\r\nxtensa_vectors.S. They are not specific to FreeRTOS, but call into\r\nFreeRTOS where appropriate via macros defined in xtensa_rtos.h .\r\n\r\n&#x5B;...]\r\n\r\nThe following subsections describe the handling of each class of exception\r\nand interrupt in more detail. Many have nothing to do with FreeRTOS but\r\nare mentioned because there is code to handle them in xtensa_vectors.S.\r\n\r\nUser Exception and Interrupt Handler (Low\/Medium Priority):\r\n\r\n    All Xtensa 'general exceptions' come to the user, kernel, or double\r\n    exception vector.  The exception type is identified by the EXCCAUSE\r\n    special register (level 1 interrupts are one particular cause of a\r\n    general exception). This port sets up PS to direct all such exceptions\r\n    to the user vector. Exceptions taken at the other two vectors usually\r\n    indicate a kernel or application bug.\r\n\r\n    Level 1 interrupts are identified at the beginning of the handler\r\n    and are dispatched to a dedicated handler. Then, syscall and alloca\r\n    exceptions are identified and dispatched to special handlers described\r\n    below. After this, coprocessor exceptions are identified and dispatched\r\n    to the coprocessor handler.\r\n\r\n    Any remaining exceptions are processed as follows:\r\n\r\n    Having allocated the exception stack frame, the user exception handler\r\n    saves the current task state and sets up a C environment and enables\r\n    the high-priority class of interrupts (which do not interact with\r\n    FreeRTOS), then reads EXCCAUSE and uses the cause (number) to index\r\n    into a table of user-specified handlers. The correct handler is then\r\n    called. If the handler returns, the context is restored and control is\r\n    returned to the code that caused the exception. The user-defined handler\r\n    may alter the saved context, or any other system state, that allows the\r\n    faulting instruction to be retried.\r\n\r\n    If the cause is a level 1 (low-priority) or medium-priority interrupt,\r\n    the handler enables all interrupts above that priority level after\r\n    saving the task context. It then sets up the environment for C code\r\n    and then calls the handler (found in the handler table) for the\r\n    interrupt number. If the user has not specified a handler, then the\r\n    default handler will be called, which will terminate the program.\r\n\r\n    If the interrupt is for the system timer, it calls a special interrupt\r\n    handler for the system timer tick, which calls _frxt_timer_int then\r\n    clears its bit from the mask. This interrupt cannot be hooked by the\r\n    user-defined handler.\r\n\r\n    Finally, the handler calls _frxt_int_exit to allow FreeRTOS to perform\r\n    any scheduling necessary and return either to the interrupted task\r\n    or another.\r\n\r\n    If software prioritization is enabled, the handler will re-enable all\r\n    interrupts at the same level that are numerically higher than the current\r\n    one, before calling the user handler. This allows a higher priority\r\n    interrupt to pre-empt the lower priority handler.\r\n\r\n&#x5B;...]\r\n\r\nMedium Priority Interrupt Handlers:\r\n\r\n    Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL,\r\n    a configuration-specific maximum interrupt level affected by the global\r\n    'exception mode' bit in the processor status word (PS.EXCM).\r\n    Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.\r\n    The Xtensa hardware documentation considers medium priority interrupts\r\n    to be a special case of high-priority interrupts, but from a software\r\n    perspective they are very different.\r\n\r\n    Dispatch of medium-priority interrupts is discussed in the section\r\n    above.\r\n\r\nHigh Priority Interrupt Handlers:\r\n\r\n    High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, \r\n    a configuration-specific maximum interrupt level affected by the \r\n    global 'exception mode' bit in the processor status word (PS.EXCM).\r\n    High priority handlers may not directly interact with FreeRTOS at all,\r\n    and are described here only for the sake of completeness. They must\r\n    be coded in assembler (may not be coded in C) and are intended to be \r\n    used for handling extremely high frequency hardware events that need\r\n    to be handled in only a few cycles. A high priority interrupt handler\r\n    may trigger a software interrupt at a medium or low priority level to\r\n    occasionally signal FreeRTOS. Please see Xtensa documentation.\r\n\r\n    There is a separate vector and a few special registers for each high\r\n    priority interrupt, providing for fast dispatch and efficient nesting\r\n    on top of lower priority interrupts. Handlers are templates included\r\n    only for the vectors that exist in your Xtensa processor configuration.\r\n    These templates are written for only one interrupt per high priority \r\n    level to minimize latency servicing very fast time-critical interrupts.\r\n    The vector code jumps to the corresponding first-level interrupt handler,\r\n    which then executes application-provided assembler code before returning\r\n    quickly to the interrupted task or lower priority handler.\r\n\r\nKernel Exception Handler:\r\n\r\n    Kernel mode is not used in this port of FreeRTOS, and therefore kernel\r\n    exceptions should not happen. A stub is provided for the vector that\r\n    triggers the debugger (if connected) or calls _xt_panic to freeze the \r\n    processor should a kernel exception occur.\r\n\r\nAlloca Exception Handler:\r\n\r\n    Alloca exceptions are generated by the 'movsp' instruction, which\r\n    is used only in the windowed ABI. Its purpose is to allocate some\r\n    space on top of the stack. Because the window hardware may have\r\n    spilled some registers to the 16 byte &quot;base save&quot; area below the\r\n    stack pointer, it is necessary to protect those values. The alloca\r\n    handler accomplishes this quickly without setting up an interrupt\r\n    frame or entering FreeRTOS, by emulating a register underflow and\r\n    re-executing 'movsp'.\r\n\r\nSyscall Exception Handler:\r\n\r\n    Syscall exceptions are generated by a 'syscall' instruction.\r\n    The windowed ABI specifies that executing this instruction with\r\n    a value of zero in register a2 must spill any unsaved registers\r\n    in the windowed register file to their pre-determined locations\r\n    on the caller's stack. The handler does exactly that, and skips\r\n    over the 'syscall' instruction before returning to the caller.\r\n    If a2 is non-zero, the handler returns a2 == -1 to the caller.\r\n\r\nCo-Processor Exception Handler:\r\n\r\n    A co-processor exception is generated when a task accesses a\r\n    co-processor that it does not &quot;own&quot;. Ownership represents which\r\n    task's state is currently in the co-processor. Co-processors are\r\n    context-switched &quot;lazily&quot; (on demand) only when a non-owning task\r\n    uses a co-processor instruction, otherwise a task retains ownership\r\n    even when it is preempted from the main processor. The co-processor\r\n    exception handler performs the context-switch and manages ownership.\r\n\r\n    Co-processors may not be used by any code outside the context of a\r\n    task. A co-processor exception triggered by code that is not part\r\n    of a running task is a fatal error and FreeRTOS for Xtensa will panic.\r\n    This restriction is intended to reduce the overhead of saving and \r\n    restoring co-processor state (which can be quite large) and in \r\n    particular remove that overhead from interrupt handlers.\r\n\r\nDebug Exception Handler:\r\n\r\n    A debug exception is caused as a result of running code, such as by\r\n    a 'break' instruction or hardware breakpoints and watchpoints, or\r\n    as a result of an external debug interrupt, such as from an OCD based\r\n    debugger or multiprocessor debug events (&quot;breakin\/breakout&quot;). If the\r\n    processor is running in OCD mode under control of an OCD-based debugger,\r\n    the trigger event immediately halts the processor and gives control to\r\n    the OCD debugger. Otherwise control is transferred to the debug vector.\r\n    The debug vector handler calls the simulator if running on the ISS,\r\n    which then takes control and interacts with any attached debugger.\r\n    If running on hardware and not in OCD mode, debug exceptions are not\r\n    expected, so the debug handler calls _xt_panic to freeze the processor.\r\n\r\nDouble Exception Handler:\r\n\r\n    A double exception is a general exception that happens while the\r\n    processor is in exception mode (PS.EXCM set), and thus indicates a\r\n    bug in kernel code. The double exception vector handler triggers\r\n    the debugger (if connected) or calls _xt_panic to freeze the \r\n    processor.\r\n\r\nWindow Overflow and Underflow Exception Handlers:\r\n\r\n    Window overflow and underflow handlers are required for use of the\r\n    windowed ABI. Each has its own dedicated vector and highly optimized\r\n    code that is independent of OS. See Xtensa documentation for details.\r\n\r\nHooks for Dynamic Installation of Handlers:\r\n\r\n    Optional hooks are provided in the user exception and low level\r\n    interrupt handler and all medium and high priority interrupt handlers,\r\n    to dynamically install a handler function (which may be coded in C,\r\n    unless in a high-priority interrupt handler). These hooks are enabled\r\n    and used by automatic regression tests, they are not part of a normal\r\n    FreeRTOS build. However an application is free to take advantage of\r\n    them. The interrupt\/exception hooks are described in xtensa_rtos.h .\r\n\r\n    It is recommended that the application not make use of these hooks, but\r\n    rather use xt_set_interrupt_handler() and xt_set_exception_handler()\r\n    to install application-specific handlers. This method is more convenient\r\n    and allows arguments to be passed to the handlers. Software prioritization\r\n    of interrupts works only with this method. See xtensa_api.h for details.\r\n\r\n&#x5B;...]\r\n<\/pre>\n<h3>MyApp<\/h3>\n<pre class=\"brush: plain; collapse: true; light: false; title: Compile MyApp; toolbar: true; notranslate\" title=\"Compile MyApp\">\r\n$ git clone https:\/\/github.com\/espressif\/esp-idf-template.git myapp\r\n$ cd myapp\r\n$ make menuconfig\r\nmake&#x5B;1]: Entering directory '\/home\/andreas\/esp32\/esp-idf\/tools\/kconfig'\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o mconf.o mconf.c\r\nflex -L -P zconf -o zconf.lex.c zconf.l\r\nzconf.l:255: warning, -s option given but default rule can be matched\r\nbison -t -l -p zconf -o zconf.tab.c zconf.y\r\nsed -E &quot;s\/\\\\x0D$\/\/&quot; zconf.gperf | gperf -t --output-file zconf.hash.c -a -C -E -g -k '1,3,$' -p -t\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o zconf.tab.o zconf.tab.c\r\nlxdialog\/check-lxdialog.sh -check cc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE -lncurses -ltinfo\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o lxdialog\/checklist.o lxdialog\/checklist.c\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o lxdialog\/util.o lxdialog\/util.c\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o lxdialog\/inputbox.o lxdialog\/inputbox.c\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o lxdialog\/textbox.o lxdialog\/textbox.c\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o lxdialog\/yesno.o lxdialog\/yesno.c\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o lxdialog\/menubox.o lxdialog\/menubox.c\r\ncc -o mconf mconf.o zconf.tab.o lxdialog\/checklist.o lxdialog\/util.o lxdialog\/inputbox.o lxdialog\/textbox.o lxdialog\/yesno.o lxdialog\/menubox.o -lncurses -ltinfo\r\ncc  -D_GNU_SOURCE -DCURSES_LOC=&quot;&lt;ncurses.h&gt;&quot; -DLOCALE   -c -o conf.o conf.c\r\ncc -o conf conf.o  zconf.tab.o -lncurses -ltinfo\r\nmake&#x5B;1]: Leaving directory '\/home\/andreas\/esp32\/esp-idf\/tools\/kconfig'\r\nMENUCONFIG\r\nconfiguration written to \/home\/andreas\/esp32\/apps\/myapp\/sdkconfig\r\n\r\n*** End of the configuration.\r\n*** Execute 'make' to start the build or try 'make help'.\r\n\r\nGENCONFIG\r\n\r\n$ make\r\nCC src\/bootloader_flash.o\r\nCC src\/efuse.o\r\nCC src\/secure_boot.o\r\nCC src\/secure_boot_signatures.o\r\nCC src\/flash_partitions.o\r\nCC src\/esp_image_format.o\r\nCC src\/flash_encrypt.o\r\nCC src\/bootloader_random.o\r\nAR libbootloader_support.a\r\nCC log.o\r\nAR liblog.a\r\nCC spi_flash_rom_patch.o\r\nAR libspi_flash.a\r\nCC micro-ecc\/uECC.o\r\nAR libmicro-ecc.a\r\nCC esp32\/rtc_pm.o\r\nCC esp32\/cpu_util.o\r\nCC esp32\/brownout.o\r\nCC esp32\/rtc_time.o\r\nCC esp32\/rtc_init.o\r\nCC esp32\/rtc_sleep.o\r\nCC esp32\/rtc_clk.o\r\nAR libsoc.a\r\nCC bootloader_start.o\r\nCC flash_qio_mode.o\r\nAR libmain.a\r\nLD bootloader.elf\r\nesptool.py v2.0.1\r\nBuilding partitions from \/home\/andreas\/esp32\/esp-idf\/components\/partition_table\/partitions_singleapp.csv...\r\nCC app_trace_util.o\r\nCC app_trace.o\r\nAR libapp_trace.a\r\nCC esp_ota_ops.o\r\nAR libapp_update.a\r\nCC src\/bootloader_flash.o\r\nCC src\/efuse.o\r\nCC src\/secure_boot.o\r\nCC src\/secure_boot_signatures.o\r\nCC src\/flash_partitions.o\r\nCC src\/esp_image_format.o\r\nCC src\/flash_encrypt.o\r\nCC src\/bootloader_random.o\r\nAR libbootloader_support.a\r\nCC bt.o\r\nCC bluedroid\/bta\/dm\/bta_dm_api.o\r\nCC bluedroid\/bta\/dm\/bta_dm_sco.o\r\nCC bluedroid\/bta\/dm\/bta_dm_ci.o\r\nCC bluedroid\/bta\/dm\/bta_dm_act.o\r\nCC bluedroid\/bta\/dm\/bta_dm_pm.o\r\nCC bluedroid\/bta\/dm\/bta_dm_main.o\r\nCC bluedroid\/bta\/dm\/bta_dm_cfg.o\r\nCC bluedroid\/bta\/gatt\/bta_gatts_main.o\r\nCC bluedroid\/bta\/gatt\/bta_gattc_cache.o\r\nCC bluedroid\/bta\/gatt\/bta_gattc_main.o\r\nCC bluedroid\/bta\/gatt\/bta_gatts_api.o\r\nCC bluedroid\/bta\/gatt\/bta_gattc_utils.o\r\nCC bluedroid\/bta\/gatt\/bta_gattc_ci.o\r\nCC bluedroid\/bta\/gatt\/bta_gattc_act.o\r\nCC bluedroid\/bta\/gatt\/bta_gattc_api.o\r\nCC bluedroid\/bta\/gatt\/bta_gatts_act.o\r\nCC bluedroid\/bta\/gatt\/bta_gatts_utils.o\r\nCC bluedroid\/bta\/hh\/bta_hh_api.o\r\nCC bluedroid\/bta\/hh\/bta_hh_utils.o\r\nCC bluedroid\/bta\/hh\/bta_hh_le.o\r\nCC bluedroid\/bta\/hh\/bta_hh_act.o\r\nCC bluedroid\/bta\/hh\/bta_hh_main.o\r\nCC bluedroid\/bta\/hh\/bta_hh_cfg.o\r\nCC bluedroid\/bta\/sdp\/bta_sdp.o\r\nCC bluedroid\/bta\/sdp\/bta_sdp_act.o\r\nCC bluedroid\/bta\/sdp\/bta_sdp_cfg.o\r\nCC bluedroid\/bta\/sdp\/bta_sdp_api.o\r\nCC bluedroid\/bta\/av\/bta_av_api.o\r\nCC bluedroid\/bta\/av\/bta_av_ssm.o\r\nCC bluedroid\/bta\/av\/bta_av_cfg.o\r\nCC bluedroid\/bta\/av\/bta_av_ci.o\r\nCC bluedroid\/bta\/av\/bta_av_act.o\r\nCC bluedroid\/bta\/av\/bta_av_main.o\r\nCC bluedroid\/bta\/av\/bta_av_sbc.o\r\nCC bluedroid\/bta\/av\/bta_av_aact.o\r\nCC bluedroid\/bta\/ar\/bta_ar.o\r\nCC bluedroid\/bta\/sys\/bta_sys_main.o\r\nCC bluedroid\/bta\/sys\/utl.o\r\nCC bluedroid\/bta\/sys\/bta_sys_conn.o\r\nCC bluedroid\/btcore\/bdaddr.o\r\nCC bluedroid\/btif\/bta_gatts_co.o\r\nCC bluedroid\/btif\/bta_dm_co.o\r\nCC bluedroid\/btif\/bta_gattc_co.o\r\nCC bluedroid\/device\/interop.o\r\nCC bluedroid\/device\/controller.o\r\nCC bluedroid\/gki\/gki_ulinux.o\r\nCC bluedroid\/gki\/gki_buffer.o\r\nCC bluedroid\/hci\/buffer_allocator.o\r\nCC bluedroid\/hci\/hci_hal_h4.o\r\nCC bluedroid\/hci\/hci_packet_parser.o\r\nCC bluedroid\/hci\/packet_fragmenter.o\r\nCC bluedroid\/hci\/hci_layer.o\r\nCC bluedroid\/hci\/hci_packet_factory.o\r\nCC bluedroid\/main\/bte_main.o\r\nCC bluedroid\/main\/bte_init.o\r\nCC bluedroid\/osi\/future.o\r\nCC bluedroid\/osi\/hash_map.o\r\nCC bluedroid\/osi\/fixed_queue.o\r\nCC bluedroid\/osi\/allocator.o\r\nCC bluedroid\/osi\/config.o\r\nCC bluedroid\/osi\/list.o\r\nCC bluedroid\/osi\/hash_functions.o\r\nCC bluedroid\/osi\/alarm.o\r\nCC bluedroid\/osi\/buffer.o\r\nCC bluedroid\/osi\/osi_arch.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/bitstream-decode.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/synthesis-sbc.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/decoder-oina.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/bitalloc.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/framing.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/dequant.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/alloc.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/synthesis-dct8.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/bitalloc-sbc.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/decoder-private.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/synthesis-8-generated.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/framing-sbc.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/oi_codec_version.o\r\nCC bluedroid\/external\/sbc\/decoder\/srce\/decoder-sbc.o\r\nCC bluedroid\/btc\/core\/btc_util.o\r\nCC bluedroid\/btc\/core\/btc_task.o\r\nCC bluedroid\/btc\/core\/btc_main.o\r\nCC bluedroid\/btc\/core\/btc_dev.o\r\nCC bluedroid\/btc\/core\/btc_storage.o\r\nCC bluedroid\/btc\/core\/btc_ble_storage.o\r\nCC bluedroid\/btc\/core\/btc_sm.o\r\nCC bluedroid\/btc\/core\/btc_profile_queue.o\r\nCC bluedroid\/btc\/core\/btc_alarm.o\r\nCC bluedroid\/btc\/core\/btc_manage.o\r\nCC bluedroid\/btc\/core\/btc_sec.o\r\nCC bluedroid\/btc\/core\/btc_config.o\r\nCC bluedroid\/btc\/core\/btc_dm.o\r\nCC bluedroid\/btc\/profile\/esp\/blufi\/blufi_prf.o\r\nCC bluedroid\/btc\/profile\/esp\/blufi\/blufi_protocol.o\r\nCC bluedroid\/btc\/profile\/std\/gap\/btc_gap_bt.o\r\nCC bluedroid\/btc\/profile\/std\/gap\/btc_gap_ble.o\r\nCC bluedroid\/btc\/profile\/std\/gatt\/btc_gatts.o\r\nCC bluedroid\/btc\/profile\/std\/gatt\/btc_gatt_util.o\r\nCC bluedroid\/btc\/profile\/std\/gatt\/btc_gattc.o\r\nCC bluedroid\/btc\/profile\/std\/a2dp\/bta_av_co.o\r\nCC bluedroid\/btc\/profile\/std\/a2dp\/btc_media_task.o\r\nCC bluedroid\/btc\/profile\/std\/a2dp\/btc_avk.o\r\nCC bluedroid\/btc\/profile\/std\/avrc\/btc_avrc.o\r\nCC bluedroid\/stack\/btm\/btm_ble_batchscan.o\r\nCC bluedroid\/stack\/btm\/btm_ble_cont_energy.o\r\nCC bluedroid\/stack\/btm\/btm_sec.o\r\nCC bluedroid\/stack\/btm\/btm_ble.o\r\nCC bluedroid\/stack\/btm\/btm_pm.o\r\nCC bluedroid\/stack\/btm\/btm_ble_adv_filter.o\r\nCC bluedroid\/stack\/btm\/btm_inq.o\r\nCC bluedroid\/stack\/btm\/btm_main.o\r\nCC bluedroid\/stack\/btm\/btm_devctl.o\r\nCC bluedroid\/stack\/btm\/btm_ble_privacy.o\r\nCC bluedroid\/stack\/btm\/btm_acl.o\r\nCC bluedroid\/stack\/btm\/btm_ble_bgconn.o\r\nCC bluedroid\/stack\/btm\/btm_dev.o\r\nCC bluedroid\/stack\/btm\/btm_ble_gap.o\r\nCC bluedroid\/stack\/btm\/btm_ble_multi_adv.o\r\nCC bluedroid\/stack\/btm\/btm_ble_addr.o\r\nCC bluedroid\/stack\/btm\/btm_sco.o\r\nCC bluedroid\/stack\/btu\/btu_hcif.o\r\nCC bluedroid\/stack\/btu\/btu_task.o\r\nCC bluedroid\/stack\/btu\/btu_init.o\r\nCC bluedroid\/stack\/gap\/gap_ble.o\r\nCC bluedroid\/stack\/gap\/gap_conn.o\r\nCC bluedroid\/stack\/gap\/gap_api.o\r\nCC bluedroid\/stack\/gap\/gap_utils.o\r\nCC bluedroid\/stack\/gatt\/gatt_db.o\r\nCC bluedroid\/stack\/gatt\/gatt_cl.o\r\nCC bluedroid\/stack\/gatt\/gatt_attr.o\r\nCC bluedroid\/stack\/gatt\/gatt_main.o\r\nCC bluedroid\/stack\/gatt\/gatt_sr.o\r\nCC bluedroid\/stack\/gatt\/att_protocol.o\r\nCC bluedroid\/stack\/gatt\/gatt_auth.o\r\nCC bluedroid\/stack\/gatt\/gatt_api.o\r\nCC bluedroid\/stack\/gatt\/gatt_utils.o\r\nCC bluedroid\/stack\/hcic\/hciblecmds.o\r\nCC bluedroid\/stack\/hcic\/hcicmds.o\r\nCC bluedroid\/stack\/l2cap\/l2c_ble.o\r\nCC bluedroid\/stack\/l2cap\/l2c_main.o\r\nCC bluedroid\/stack\/l2cap\/l2c_utils.o\r\nCC bluedroid\/stack\/l2cap\/l2c_ucd.o\r\nCC bluedroid\/stack\/l2cap\/l2c_api.o\r\nCC bluedroid\/stack\/l2cap\/l2cap_client.o\r\nCC bluedroid\/stack\/l2cap\/l2c_csm.o\r\nCC bluedroid\/stack\/l2cap\/l2c_link.o\r\nCC bluedroid\/stack\/l2cap\/l2c_fcr.o\r\nCC bluedroid\/stack\/sdp\/sdp_utils.o\r\nCC bluedroid\/stack\/sdp\/sdp_db.o\r\nCC bluedroid\/stack\/sdp\/sdp_discovery.o\r\nCC bluedroid\/stack\/sdp\/sdp_main.o\r\nCC bluedroid\/stack\/sdp\/sdp_server.o\r\nCC bluedroid\/stack\/sdp\/sdp_api.o\r\nCC bluedroid\/stack\/smp\/p_256_curvepara.o\r\nCC bluedroid\/stack\/smp\/smp_api.o\r\nCC bluedroid\/stack\/smp\/smp_utils.o\r\nCC bluedroid\/stack\/smp\/p_256_ecc_pp.o\r\nCC bluedroid\/stack\/smp\/smp_act.o\r\nCC bluedroid\/stack\/smp\/smp_cmac.o\r\nCC bluedroid\/stack\/smp\/smp_keys.o\r\nCC bluedroid\/stack\/smp\/smp_br_main.o\r\nCC bluedroid\/stack\/smp\/aes.o\r\nCC bluedroid\/stack\/smp\/smp_main.o\r\nCC bluedroid\/stack\/smp\/p_256_multprecision.o\r\nCC bluedroid\/stack\/smp\/smp_l2c.o\r\nCC bluedroid\/stack\/avct\/avct_lcb.o\r\nCC bluedroid\/stack\/avct\/avct_lcb_act.o\r\nCC bluedroid\/stack\/avct\/avct_l2c.o\r\nCC bluedroid\/stack\/avct\/avct_api.o\r\nCC bluedroid\/stack\/avct\/avct_ccb.o\r\nCC bluedroid\/stack\/avrc\/avrc_pars_ct.o\r\nCC bluedroid\/stack\/avrc\/avrc_opt.o\r\nCC bluedroid\/stack\/avrc\/avrc_bld_ct.o\r\nCC bluedroid\/stack\/avrc\/avrc_pars_tg.o\r\nCC bluedroid\/stack\/avrc\/avrc_bld_tg.o\r\nCC bluedroid\/stack\/avrc\/avrc_api.o\r\nCC bluedroid\/stack\/avrc\/avrc_utils.o\r\nCC bluedroid\/stack\/avrc\/avrc_sdp.o\r\nCC bluedroid\/stack\/avdt\/avdt_l2c.o\r\nCC bluedroid\/stack\/avdt\/avdt_api.o\r\nCC bluedroid\/stack\/avdt\/avdt_scb.o\r\nCC bluedroid\/stack\/avdt\/avdt_ccb_act.o\r\nCC bluedroid\/stack\/avdt\/avdt_ccb.o\r\nCC bluedroid\/stack\/avdt\/avdt_msg.o\r\nCC bluedroid\/stack\/avdt\/avdt_scb_act.o\r\nCC bluedroid\/stack\/avdt\/avdt_ad.o\r\nCC bluedroid\/stack\/a2dp\/a2d_sbc.o\r\nCC bluedroid\/stack\/a2dp\/a2d_api.o\r\nCC bluedroid\/utils\/bt_utils.o\r\nCC bluedroid\/api\/esp_avrc_api.o\r\nCC bluedroid\/api\/esp_bt_main.o\r\nCC bluedroid\/api\/esp_bt_device.o\r\nCC bluedroid\/api\/esp_gap_bt_api.o\r\nCC bluedroid\/api\/esp_a2dp_api.o\r\nCC bluedroid\/api\/esp_gattc_api.o\r\nCC bluedroid\/api\/esp_blufi_api.o\r\nCC bluedroid\/api\/esp_gap_ble_api.o\r\nCC bluedroid\/api\/esp_gatts_api.o\r\nAR libbt.a\r\nCC libcoap\/src\/address.o\r\nCC libcoap\/src\/async.o\r\nCC libcoap\/src\/block.o\r\nCC libcoap\/src\/coap_time.o\r\nCC libcoap\/src\/debug.o\r\nCC libcoap\/src\/encode.o\r\nCC libcoap\/src\/hashkey.o\r\nCC libcoap\/src\/mem.o\r\nCC libcoap\/src\/net.o\r\nCC libcoap\/src\/option.o\r\nCC libcoap\/src\/pdu.o\r\nCC libcoap\/src\/resource.o\r\nCC libcoap\/src\/str.o\r\nCC libcoap\/src\/subscribe.o\r\nCC libcoap\/src\/uri.o\r\nCC port\/coap_io_socket.o\r\nAR libcoap.a\r\nCXX cxx_guards.o\r\nAR libcxx.a\r\nCC spi_master.o\r\nCC sigmadelta.o\r\nCC uart.o\r\nCC i2c.o\r\nCC periph_ctrl.o\r\nCC ledc.o\r\nCC spi_common.o\r\nCC gpio.o\r\nCC pcnt.o\r\nCC timer.o\r\nCC rmt.o\r\nCC mcpwm.o\r\nCC sdmmc_transaction.o\r\nCC spi_slave.o\r\nCC sdmmc_host.o\r\nCC i2s.o\r\nCC rtc_module.o\r\nAR libdriver.a\r\nCC panic.o\r\nCC core_dump.o\r\nCC lib_printf.o\r\nCC task_wdt.o\r\nCC cpu_start.o\r\nCC restore.o\r\nCC crosscore_int.o\r\nCC phy_init.o\r\nCC deep_sleep.o\r\nCC clk.o\r\nCC freertos_hooks.o\r\nCC gdbstub.o\r\nCC cache_err_int.o\r\nCC ipc.o\r\nCC intr_alloc.o\r\nCC heap_alloc_caps.o\r\nCC int_wdt.o\r\nCC event_loop.o\r\nCC hw_random.o\r\nCC dport_access.o\r\nCC system_api.o\r\nCC event_default_handlers.o\r\nCC hwcrypto\/sha.o\r\nCC hwcrypto\/aes.o\r\nAR libesp32.a\r\nCC emac_dev.o\r\nCC emac_main.o\r\nCC eth_phy\/phy_common.o\r\nCC eth_phy\/phy_lan8720.o\r\nCC eth_phy\/phy_tlk110.o\r\nAR libethernet.a\r\nCC library\/xmltok_ns.o\r\nCC library\/xmlparse.o\r\nCC library\/xmltok.o\r\nCC library\/xmlrole.o\r\nCC library\/xmltok_impl.o\r\nCC port\/minicheck.o\r\nCC port\/expat_element.o\r\nCC port\/chardata.o\r\nAR libexpat.a\r\nCC src\/option\/syscall.o\r\nCC src\/option\/unicode.o\r\nCC src\/ff.o\r\nCC src\/vfs_fat_sdmmc.o\r\nCC src\/diskio_sdmmc.o\r\nCC src\/vfs_fat_spiflash.o\r\nCC src\/diskio_spiflash.o\r\nCC src\/vfs_fat.o\r\nCC src\/diskio.o\r\nAR libfatfs.a\r\nCC ringbuf.o\r\nCC heap_regions_debug.o\r\nCC xtensa_intr.o\r\nCC queue.o\r\nCC croutine.o\r\nCC list.o\r\nCC xtensa_init.o\r\nCC port.o\r\nCC heap_regions.o\r\nCC event_groups.o\r\nCC tasks.o\r\nCC timers.o\r\nCC FreeRTOS-openocd.o\r\nCC xtensa_overlay_os_hook.o\r\nAS xtensa_intr_asm.o\r\nAS xtensa_context.o\r\nAS xtensa_vectors.o\r\nAS portasm.o\r\nAR libfreertos.a\r\nCC src\/\/jsmn.o\r\nAR libjsmn.a\r\nCC library\/cJSON.o\r\nCC port\/cJSON_Utils.o\r\nAR libjson.a\r\nCC private\/randombytes_esp32.o\r\nCC libsodium\/src\/libsodium\/crypto_aead\/chacha20poly1305\/sodium\/aead_chacha20poly1305.o\r\nCC libsodium\/src\/libsodium\/crypto_aead\/xchacha20poly1305\/sodium\/aead_xchacha20poly1305.o\r\nCC libsodium\/src\/libsodium\/crypto_auth\/crypto_auth.o\r\nCC libsodium\/src\/libsodium\/crypto_auth\/hmacsha256\/auth_hmacsha256.o\r\nCC libsodium\/src\/libsodium\/crypto_auth\/hmacsha512\/auth_hmacsha512.o\r\nCC libsodium\/src\/libsodium\/crypto_auth\/hmacsha512256\/auth_hmacsha512256.o\r\nCC libsodium\/src\/libsodium\/crypto_box\/crypto_box_seal.o\r\nCC libsodium\/src\/libsodium\/crypto_box\/crypto_box.o\r\nCC libsodium\/src\/libsodium\/crypto_box\/crypto_box_easy.o\r\nCC libsodium\/src\/libsodium\/crypto_box\/curve25519xsalsa20poly1305\/box_curve25519xsalsa20poly1305.o\r\nCC libsodium\/src\/libsodium\/crypto_core\/curve25519\/ref10\/curve25519_ref10.o\r\nCC libsodium\/src\/libsodium\/crypto_core\/hchacha20\/core_hchacha20.o\r\nCC libsodium\/src\/libsodium\/crypto_core\/hsalsa20\/ref2\/core_hsalsa20_ref2.o\r\nCC libsodium\/src\/libsodium\/crypto_core\/hsalsa20\/core_hsalsa20.o\r\nCC libsodium\/src\/libsodium\/crypto_core\/salsa\/ref\/core_salsa_ref.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/crypto_generichash.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/blake2b\/generichash_blake2.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/blake2b\/ref\/blake2b-compress-avx2.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/blake2b\/ref\/generichash_blake2b.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/blake2b\/ref\/blake2b-compress-ref.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/blake2b\/ref\/blake2b-compress-ssse3.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/blake2b\/ref\/blake2b-ref.o\r\nCC libsodium\/src\/libsodium\/crypto_generichash\/blake2b\/ref\/blake2b-compress-sse41.o\r\nCC libsodium\/src\/libsodium\/crypto_hash\/crypto_hash.o\r\nCC libsodium\/src\/libsodium\/crypto_hash\/sha256\/hash_sha256.o\r\nCC libsodium\/src\/libsodium\/crypto_hash\/sha256\/cp\/hash_sha256_cp.o\r\nCC libsodium\/src\/libsodium\/crypto_hash\/sha512\/hash_sha512.o\r\nCC libsodium\/src\/libsodium\/crypto_hash\/sha512\/cp\/hash_sha512_cp.o\r\nCC libsodium\/src\/libsodium\/crypto_kdf\/blake2b\/kdf_blake2b.o\r\nCC libsodium\/src\/libsodium\/crypto_kdf\/crypto_kdf.o\r\nCC libsodium\/src\/libsodium\/crypto_kx\/crypto_kx.o\r\nCC libsodium\/src\/libsodium\/crypto_onetimeauth\/crypto_onetimeauth.o\r\nCC libsodium\/src\/libsodium\/crypto_onetimeauth\/poly1305\/onetimeauth_poly1305.o\r\nCC libsodium\/src\/libsodium\/crypto_onetimeauth\/poly1305\/donna\/poly1305_donna.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/argon2\/argon2-core.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/argon2\/blake2b-long.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/argon2\/argon2-fill-block-ref.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/argon2\/argon2-encoding.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/argon2\/pwhash_argon2i.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/argon2\/argon2-fill-block-ssse3.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/argon2\/argon2.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/crypto_pwhash.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/scryptsalsa208sha256\/scrypt_platform.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/scryptsalsa208sha256\/pwhash_scryptsalsa208sha256.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/scryptsalsa208sha256\/crypto_scrypt-common.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/scryptsalsa208sha256\/pbkdf2-sha256.o\r\nCC libsodium\/src\/libsodium\/crypto_pwhash\/scryptsalsa208sha256\/nosse\/pwhash_scryptsalsa208sha256_nosse.o\r\nCC libsodium\/src\/libsodium\/crypto_scalarmult\/crypto_scalarmult.o\r\nCC libsodium\/src\/libsodium\/crypto_scalarmult\/curve25519\/scalarmult_curve25519.o\r\nCC libsodium\/src\/libsodium\/crypto_scalarmult\/curve25519\/ref10\/x25519_ref10.o\r\nCC libsodium\/src\/libsodium\/crypto_secretbox\/crypto_secretbox_easy.o\r\nCC libsodium\/src\/libsodium\/crypto_secretbox\/crypto_secretbox.o\r\nCC libsodium\/src\/libsodium\/crypto_secretbox\/xsalsa20poly1305\/secretbox_xsalsa20poly1305.o\r\nCC libsodium\/src\/libsodium\/crypto_shorthash\/crypto_shorthash.o\r\nCC libsodium\/src\/libsodium\/crypto_shorthash\/siphash24\/shorthash_siphashx24.o\r\nCC libsodium\/src\/libsodium\/crypto_shorthash\/siphash24\/shorthash_siphash24.o\r\nCC libsodium\/src\/libsodium\/crypto_shorthash\/siphash24\/ref\/shorthash_siphash24_ref.o\r\nCC libsodium\/src\/libsodium\/crypto_shorthash\/siphash24\/ref\/shorthash_siphashx24_ref.o\r\nCC libsodium\/src\/libsodium\/crypto_sign\/crypto_sign.o\r\nCC libsodium\/src\/libsodium\/crypto_sign\/ed25519\/sign_ed25519.o\r\nCC libsodium\/src\/libsodium\/crypto_sign\/ed25519\/ref10\/obsolete.o\r\nCC libsodium\/src\/libsodium\/crypto_sign\/ed25519\/ref10\/sign.o\r\nCC libsodium\/src\/libsodium\/crypto_sign\/ed25519\/ref10\/open.o\r\nCC libsodium\/src\/libsodium\/crypto_sign\/ed25519\/ref10\/keypair.o\r\nCC libsodium\/src\/libsodium\/crypto_stream\/chacha20\/stream_chacha20.o\r\nCC libsodium\/src\/libsodium\/crypto_stream\/chacha20\/ref\/chacha20_ref.o\r\nCC libsodium\/src\/libsodium\/crypto_stream\/crypto_stream.o\r\nCC libsodium\/src\/libsodium\/crypto_stream\/salsa20\/stream_salsa20.o\r\nCC libsodium\/src\/libsodium\/crypto_stream\/salsa20\/ref\/salsa20_ref.o\r\nCC libsodium\/src\/libsodium\/crypto_stream\/xsalsa20\/stream_xsalsa20.o\r\nCC libsodium\/src\/libsodium\/crypto_verify\/sodium\/verify.o\r\nCC libsodium\/src\/libsodium\/randombytes\/randombytes.o\r\nCC libsodium\/src\/libsodium\/sodium\/core.o\r\nCC libsodium\/src\/libsodium\/sodium\/version.o\r\nCC libsodium\/src\/libsodium\/sodium\/runtime.o\r\nCC libsodium\/src\/libsodium\/sodium\/utils.o\r\nAR liblibsodium.a\r\nCC log.o\r\nAR liblog.a\r\nCC api\/pppapi.o\r\nCC api\/netdb.o\r\nCC api\/api_lib.o\r\nCC api\/netifapi.o\r\nCC api\/tcpip.o\r\nCC api\/netbuf.o\r\nCC api\/err.o\r\nCC api\/api_msg.o\r\nCC api\/sockets.o\r\nCC apps\/dhcpserver.o\r\nCC apps\/sntp\/sntp.o\r\nCC apps\/ping\/ping.o\r\nCC apps\/ping\/esp_ping.o\r\nCC core\/mem.o\r\nCC core\/inet_chksum.o\r\nCC core\/init.o\r\nCC core\/memp.o\r\nCC core\/sys.o\r\nCC core\/tcp_in.o\r\nCC core\/dns.o\r\nCC core\/ip.o\r\nCC core\/raw.o\r\nCC core\/tcp.o\r\nCC core\/pbuf.o\r\nCC core\/netif.o\r\nCC core\/stats.o\r\nCC core\/timers.o\r\nCC core\/def.o\r\nCC core\/udp.o\r\nCC core\/tcp_out.o\r\nCC core\/ipv4\/ip_frag.o\r\nCC core\/ipv4\/dhcp.o\r\nCC core\/ipv4\/ip4_addr.o\r\nCC core\/ipv4\/igmp.o\r\nCC core\/ipv4\/ip4.o\r\nCC core\/ipv4\/autoip.o\r\nCC core\/ipv4\/icmp.o\r\nCC core\/ipv6\/ip6_frag.o\r\nCC core\/ipv6\/dhcp6.o\r\nCC core\/ipv6\/inet6.o\r\nCC core\/ipv6\/ip6_addr.o\r\nCC core\/ipv6\/ip6.o\r\nCC core\/ipv6\/nd6.o\r\nCC core\/ipv6\/mld6.o\r\nCC core\/ipv6\/ethip6.o\r\nCC core\/ipv6\/icmp6.o\r\nCC netif\/slipif.o\r\nCC netif\/etharp.o\r\nCC netif\/ethernet.o\r\nCC netif\/lowpan6.o\r\nCC netif\/ethernetif.o\r\nCC port\/freertos\/sys_arch.o\r\nCC port\/netif\/wlanif.o\r\nCC port\/netif\/ethernetif.o\r\nCC port\/debug\/lwip_debug.o\r\nAR liblwip.a\r\nCC library\/x509write_crt.o\r\nCC library\/pk_wrap.o\r\nCC library\/ecp_curves.o\r\nCC library\/sha512.o\r\nCC library\/pkcs12.o\r\nCC library\/ccm.o\r\nCC library\/md.o\r\nCC library\/sha1.o\r\nCC library\/x509_csr.o\r\nCC library\/ssl_cli.o\r\nCC library\/camellia.o\r\nCC library\/blowfish.o\r\nCC library\/x509.o\r\nCC library\/ssl_ticket.o\r\nCC library\/error.o\r\nCC library\/dhm.o\r\nCC library\/entropy_poll.o\r\nCC library\/cipher.o\r\nCC library\/version_features.o\r\nCC library\/ripemd160.o\r\nCC library\/rsa.o\r\nCC library\/net.o\r\nCC library\/entropy.o\r\nCC library\/md_wrap.o\r\nCC library\/pkwrite.o\r\nCC library\/ecp.o\r\nCC library\/asn1parse.o\r\nCC library\/padlock.o\r\nCC library\/ssl_ciphersuites.o\r\nCC library\/pem.o\r\nCC library\/version.o\r\nCC library\/ssl_cache.o\r\nCC library\/memory_buffer_alloc.o\r\nCC library\/md2.o\r\nCC library\/ecdsa.o\r\nCC library\/ssl_srv.o\r\nCC library\/x509_crt.o\r\nCC library\/ecdh.o\r\nCC library\/asn1write.o\r\nCC library\/md4.o\r\nCC library\/sha256.o\r\nCC library\/x509_create.o\r\nCC library\/ecjpake.o\r\nCC library\/oid.o\r\nCC library\/pkcs5.o\r\nCC library\/pkcs11.o\r\nCC library\/base64.o\r\nCC library\/xtea.o\r\nCC library\/ctr_drbg.o\r\nCC library\/cipher_wrap.o\r\nCC library\/arc4.o\r\nCC library\/bignum.o\r\nCC library\/pkparse.o\r\nCC library\/ssl_tls.o\r\nCC library\/debug.o\r\nCC library\/threading.o\r\nCC library\/x509_crl.o\r\nCC library\/gcm.o\r\nCC library\/havege.o\r\nCC library\/timing.o\r\nCC library\/certs.o\r\nCC library\/md5.o\r\nCC library\/ssl_cookie.o\r\nCC library\/aesni.o\r\nCC library\/hmac_drbg.o\r\nCC library\/des.o\r\nCC library\/x509write_csr.o\r\nCC library\/pk.o\r\nCC library\/platform.o\r\nCC library\/aes.o\r\nCC port\/mbedtls_debug.o\r\nCC port\/esp_sha1.o\r\nCC port\/net.o\r\nCC port\/esp_sha256.o\r\nCC port\/esp_bignum.o\r\nCC port\/esp_hardware.o\r\nCC port\/esp_sha512.o\r\nAR libmbedtls.a\r\nCC mdns.o\r\nAR libmdns.a\r\nCC micro-ecc\/uECC.o\r\nAR libmicro-ecc.a\r\nCC time.o\r\nCC reent_init.o\r\nCC syscalls.o\r\nCC syscall_table.o\r\nCC locks.o\r\nAR libnewlib.a\r\nCC nghttp2\/lib\/nghttp2_http.o\r\nCC nghttp2\/lib\/nghttp2_version.o\r\nCC nghttp2\/lib\/nghttp2_mem.o\r\nCC nghttp2\/lib\/nghttp2_hd_huffman.o\r\nCC nghttp2\/lib\/nghttp2_session.o\r\nCC nghttp2\/lib\/nghttp2_callbacks.o\r\nCC nghttp2\/lib\/nghttp2_outbound_item.o\r\nCC nghttp2\/lib\/nghttp2_stream.o\r\nCC nghttp2\/lib\/nghttp2_hd.o\r\nCC nghttp2\/lib\/nghttp2_priority_spec.o\r\nCC nghttp2\/lib\/nghttp2_buf.o\r\nCC nghttp2\/lib\/nghttp2_option.o\r\nCC nghttp2\/lib\/nghttp2_npn.o\r\nCC nghttp2\/lib\/nghttp2_rcbuf.o\r\nCC nghttp2\/lib\/nghttp2_helper.o\r\nCC nghttp2\/lib\/nghttp2_frame.o\r\nCC nghttp2\/lib\/nghttp2_hd_huffman_data.o\r\nCC nghttp2\/lib\/nghttp2_debug.o\r\nCC nghttp2\/lib\/nghttp2_submit.o\r\nCC nghttp2\/lib\/nghttp2_pq.o\r\nCC nghttp2\/lib\/nghttp2_queue.o\r\nCC nghttp2\/lib\/nghttp2_map.o\r\nAR libnghttp.a\r\nCXX src\/nvs_types.o\r\nCXX src\/nvs_page.o\r\nCXX src\/nvs_item_hash_list.o\r\nCXX src\/nvs_pagemanager.o\r\nCXX src\/nvs_storage.o\r\nCXX src\/nvs_api.o\r\nAR libnvs_flash.a\r\nCC library\/ssl_cert.o\r\nCC library\/ssl_methods.o\r\nCC library\/ssl_pkey.o\r\nCC library\/ssl_x509.o\r\nCC library\/ssl_lib.o\r\nCC library\/ssl_stack.o\r\nCC platform\/ssl_pm.o\r\nCC platform\/ssl_port.o\r\nAR libopenssl.a\r\nCC sdmmc_cmd.o\r\nAR libsdmmc.a\r\nCC esp32\/rtc_pm.o\r\nCC esp32\/cpu_util.o\r\nCC esp32\/brownout.o\r\nCC esp32\/rtc_time.o\r\nCC esp32\/rtc_init.o\r\nCC esp32\/rtc_sleep.o\r\nCC esp32\/rtc_clk.o\r\nAR libsoc.a\r\nCC flash_mmap.o\r\nCC partition.o\r\nCC spi_flash_rom_patch.o\r\nCC cache_utils.o\r\nCC flash_ops.o\r\nAR libspi_flash.a\r\nCC tcpip_adapter_lwip.o\r\nAR libtcpip_adapter.a\r\nCC ulp.o\r\nCC ulp_macro.o\r\nAR libulp.a\r\nCC vfs_uart.o\r\nCC vfs.o\r\nAR libvfs.a\r\nCXX wear_levelling.o\r\nCXX WL_Flash.o\r\nCXX crc32.o\r\nCXX SPI_Flash.o\r\nCXX Partition.o\r\nAR libwear_levelling.a\r\nCC src\/crypto\/aes-internal-enc.o\r\nCC src\/crypto\/sha256-internal.o\r\nCC src\/crypto\/md5-internal.o\r\nCC src\/crypto\/aes-internal.o\r\nCC src\/crypto\/sha1.o\r\nCC src\/crypto\/aes-internal-dec.o\r\nCC src\/crypto\/aes-unwrap.o\r\nCC src\/crypto\/crypto_internal-rsa.o\r\nCC src\/crypto\/des-internal.o\r\nCC src\/crypto\/dh_group5.o\r\nCC src\/crypto\/ms_funcs.o\r\nCC src\/crypto\/aes-wrap.o\r\nCC src\/crypto\/sha1-internal.o\r\nCC src\/crypto\/md4-internal.o\r\nCC src\/crypto\/dh_groups.o\r\nCC src\/crypto\/crypto_internal.o\r\nCC src\/crypto\/sha256.o\r\nCC src\/crypto\/rc4.o\r\nCC src\/crypto\/md5.o\r\nCC src\/crypto\/aes-cbc.o\r\nCC src\/crypto\/sha1-pbkdf2.o\r\nCC src\/crypto\/bignum.o\r\nCC src\/crypto\/crypto_internal-modexp.o\r\nCC src\/crypto\/crypto_internal-cipher.o\r\nCC port\/os_xtensa.o\r\nAR libwpa_supplicant.a\r\nCC eri.o\r\nCC trax.o\r\nAR libxtensa-debug-module.a\r\nCC main.o\r\nAR libmain.a\r\nLD app-template.elf\r\nesptool.py v2.0.1\r\nTo flash all build output, run 'make flash' or:\r\npython \/home\/andreas\/esp32\/esp-idf\/components\/esptool_py\/esptool\/esptool.py --chip esp32 --port \/dev\/ttyUSB0 --baud 115200 --before default_reset --after hard_reset write_flash -u --flash_mode dio --flash_freq 40m --flash_size detect 0x1000 \/home\/andreas\/esp32\/apps\/myapp\/build\/bootloader\/bootloader.bin 0x10000 \/home\/andreas\/esp32\/apps\/myapp\/build\/app-template.bin 0x8000 \/home\/andreas\/esp32\/apps\/myapp\/build\/partitions_singleapp.bin\r\n<\/pre>\n<h3>GNU ld<\/h3>\n<pre class=\"brush: plain; collapse: true; light: false; title: GNU ld internal linker script; toolbar: true; notranslate\" title=\"GNU ld internal linker script\">\r\n$ .\/xtensa-esp32-elf-gcc a.c -Wl,-verbose\r\nGNU ld (crosstool-NG crosstool-ng-1.22.0-61-gab8375a) 2.25.1\r\n  Supported emulations:\r\n   elf32xtensa\r\nusing internal linker script:\r\n==================================================\r\n\/* Script for -z combreloc: combine and sort reloc sections *\/\r\n\/* Copyright (C) 2014 Free Software Foundation, Inc.\r\n   Copying and distribution of this script, with or without modification,\r\n   are permitted in any medium without royalty provided the copyright\r\n   notice and this notice are preserved.  *\/\r\nENTRY(_start)\r\nSEARCH_DIR(&quot;=\/home\/ivan\/e\/crosstool-NG\/builds\/xtensa-esp32-elf\/xtensa-esp32-elf\/lib&quot;); SEARCH_DIR(&quot;=\/usr\/local\/lib&quot;); SEARCH_DIR(&quot;=\/lib&quot;); SEARCH_DIR(&quot;=\/usr\/lib&quot;);\r\nSECTIONS\r\n{\r\n  \/* Read-only sections, merged into text segment: *\/\r\n  PROVIDE (__executable_start = 0x400000); . = 0x400000 + SIZEOF_HEADERS;\r\n  .interp         : { *(.interp) }\r\n  .note.gnu.build-id : { *(.note.gnu.build-id) }\r\n  .hash           : { *(.hash) }\r\n  .gnu.hash       : { *(.gnu.hash) }\r\n  .dynsym         : { *(.dynsym) }\r\n  .dynstr         : { *(.dynstr) }\r\n  .gnu.version    : { *(.gnu.version) }\r\n  .gnu.version_d  : { *(.gnu.version_d) }\r\n  .gnu.version_r  : { *(.gnu.version_r) }\r\n  .rela.dyn       :\r\n    {\r\n      *(.rela.init)\r\n      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)\r\n      *(.rela.fini)\r\n      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)\r\n      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)\r\n      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)\r\n      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)\r\n      *(.rela.ctors)\r\n      *(.rela.dtors)\r\n      *(.rela.got)\r\n      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)\r\n    }\r\n  .rela.plt       : { *(.rela.plt) }\r\n  \/* .plt* sections are embedded in .text *\/\r\n  .text           :\r\n  {\r\n    *(.got.plt* .plt*)\r\n    KEEP (*(.init.literal))\r\n    KEEP (*(SORT_NONE(.init)))\r\n    *(.literal .text .stub .literal.* .text.* .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)\r\n    \/* .gnu.warning sections are handled specially by elf32.em.  *\/\r\n    *(.gnu.warning)\r\n    KEEP (*(.fini.literal))\r\n    KEEP (*(SORT_NONE(.fini)))\r\n  } =0\r\n  PROVIDE (__etext = .);\r\n  PROVIDE (_etext = .);\r\n  PROVIDE (etext = .);\r\n  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }\r\n  .rodata1        : { *(.rodata1) }\r\n  .got.loc        : { *(.got.loc) }\r\n  .xt_except_table   : ONLY_IF_RO { KEEP (*(.xt_except_table .xt_except_table.* .gnu.linkonce.e.*)) }\r\n  .eh_frame_hdr : { *(.eh_frame_hdr) }\r\n  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }\r\n  .gcc_except_table   : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) }\r\n  \/* Adjust the address for the data segment.  We want to adjust up to\r\n     the same address within the page on the next page up.  *\/\r\n  . = ALIGN(CONSTANT (MAXPAGESIZE)) + (. &amp; (CONSTANT (MAXPAGESIZE) - 1));\r\n  \/* Exception handling  *\/\r\n  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }\r\n  .gcc_except_table   : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }\r\n  \/* Thread Local Storage sections  *\/\r\n  .tdata\t  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }\r\n  .tbss\t\t  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }\r\n  .preinit_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__preinit_array_start = .);\r\n    KEEP (*(.preinit_array))\r\n    PROVIDE_HIDDEN (__preinit_array_end = .);\r\n  }\r\n  .init_array     :\r\n  {\r\n     PROVIDE_HIDDEN (__init_array_start = .);\r\n     KEEP (*(SORT(.init_array.*)))\r\n     KEEP (*(.init_array))\r\n     PROVIDE_HIDDEN (__init_array_end = .);\r\n  }\r\n  .fini_array     :\r\n  {\r\n    PROVIDE_HIDDEN (__fini_array_start = .);\r\n    KEEP (*(SORT(.fini_array.*)))\r\n    KEEP (*(.fini_array))\r\n    PROVIDE_HIDDEN (__fini_array_end = .);\r\n  }\r\n  .ctors          :\r\n  {\r\n    \/* gcc uses crtbegin.o to find the start of\r\n       the constructors, so we make sure it is\r\n       first.  Because this is a wildcard, it\r\n       doesn't matter if the user does not\r\n       actually link against crtbegin.o; the\r\n       linker won't look for a file to match a\r\n       wildcard.  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Align after .bss to ensure correct alignment even if the\r\n      .bss section disappears because there are no input sections.\r\n      FIXME: Why do we need it? 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ESP-IDF, multicore &#038; freeRTOS confusion To [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-6296","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/6296","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=6296"}],"version-history":[{"count":94,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/6296\/revisions"}],"predecessor-version":[{"id":13848,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/6296\/revisions\/13848"}],"wp:attachment":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=6296"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=6296"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=6296"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}