{"id":1696,"date":"2014-01-15T16:06:42","date_gmt":"2014-01-15T16:06:42","guid":{"rendered":"http:\/\/blog.bachi.net\/?p=1696"},"modified":"2014-01-28T09:29:29","modified_gmt":"2014-01-28T09:29:29","slug":"vhdl-constructions","status":"publish","type":"post","link":"https:\/\/blog.bachi.net\/?p=1696","title":{"rendered":"VHDL Constructions"},"content":{"rendered":"<p><a href=\"http:\/\/www.altera.com\/support\/examples\/vhdl\/vhdl.html\">Altera VHDL Examples<\/a><br \/>\n<a href=\"https:\/\/www.itiv.kit.edu\/english\/729.php\">Die Hardwarebeschreibungssprache VHDL<\/a><br \/>\n<a href=\"http:\/\/opencores.org\/\">OpenCores open source hardware IP-cores<\/a><\/p>\n<h5>RegEx Look-around assertions<\/h5>\n<p>Diese Konstrukte erweitern die regul\u00e4ren Ausdr\u00fccke um die M\u00f6glichkeit, kontextsensitive Bedingungen zu formulieren, ohne den Kontext selbst zu matchen.<br \/>\nDas hei\u00dft, m\u00f6chte man alle Zeichenfolgen \u201eSport\u201c matchen, denen die Zeichenfolge \u201everein\u201c folgt, ohne dass jedoch die gematchte Zeichenfolge die Zeichenfolge \u201everein\u201c selbst enth\u00e4lt, w\u00e4re dies mit einer look-ahead assertion m\u00f6glich: Sport(?=verein)<\/p>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\n(?&lt;=(\\s|^))entity(?=(\\s|$))\r\n\r\n(?&lt;=Ausdruck) = positive look-behind assertion\r\n(?=Ausdruck)  = positive look-ahead assertion\r\n\r\nAlt (nicht verwenden!):\r\n(&#x5B;^a-z]*|^)entity(&#x5B;^a-z]*|\\w|$)\r\n(&#x5B;^a-z ]+|^)entity(&#x5B;^a-z ]+|\\w|$)\r\n<\/pre>\n<h2>VHDL<\/h2>\n<p><a href=\"http:\/\/www.csee.umbc.edu\/portal\/help\/VHDL\/design.html#spec\">VHDL Design Units and Subprograms<\/a><br \/>\n<a href=\"http:\/\/webdocs.cs.ualberta.ca\/~amaral\/courses\/329\/labs\/VHDL_Guideline.html\">VHDL Coding Style Guidelines<\/a><\/p>\n<h4>Package<\/h4>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\npackage &lt;PACKAGE_NAME&gt; is\r\n    &#x5B;...]\r\nend package &lt;PACKAGE_NAME&gt;;\r\n\r\npackage body &lt;PACKAGE_NAME&gt; is\r\n    &#x5B;...]\r\nend package body &lt;PACKAGE_NAME&gt;;\r\n<\/pre>\n<p><a href=\"http:\/\/www.sigasi.com\/content\/use-and-library-vhdl\">&#8220;Use&#8221; and &#8220;Library&#8221; in VHDL<\/a><br \/>\n<a href=\"http:\/\/www.arl.wustl.edu\/projects\/fpx\/class\/resources\/Libraries%20and%20Packages%20in%20VHDL.htm\">Libraries and Packages in VHDL<\/a><br \/>\n<a href=\"http:\/\/electronics.stackexchange.com\/questions\/16692\/vhdl-component-vs-entity\">VHDL: Component vs Entity<\/a><br \/>\n<a href=\"http:\/\/www.makestuff.eu\/wordpress\/vhdl-packages\/\">VHDL Packages<\/a><br \/>\n<a href=\"http:\/\/www.sigasi.com\/content\/work-not-vhdl-library\">WORK is not a VHDL Library<\/a><\/p>\n<h4>Function<\/h4>\n<pre class=\"brush: plain; title: Syntax; notranslate\" title=\"Syntax\">\r\nfunction function_name (parameter_list) return type is  \r\nbegin\r\n    &#x5B;...]\r\nend function_name;\r\n<\/pre>\n<pre class=\"brush: plain; title: Example; notranslate\" title=\"Example\">\r\nfunction shift_rows (\r\n    X : std_logic;\r\n    Y : std_logic;\r\n    Z : std_logic\r\n) return std_logic is  \r\nbegin\r\n    &#x5B;...]\r\nend shift_rows;\r\n\r\nencrypt_block : process(reset_50_n,clock_50_i)\r\n        variable temp_state;\r\n<\/pre>\n<h4>Procedure<\/h4>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\nprocedure &lt;PROCEDURE_NAME&gt; (    \r\n    X : std_logic;\r\n    Y : std_logic;\r\n    Z : std_logic\r\n) is\r\n\tdeclarations\r\nbegin\r\n\tsequential statements\r\nend procedure_name;\r\n<\/pre>\n<p>    type path_record_i  is record<br \/>\n        data                                                : std_logic_vector((PATH_DATA_WIDTH_IN_BITS-1) downto 0);<br \/>\n        clk                                                 : std_logic;<br \/>\n        dv                                                  : std_logic;<br \/>\n        err                                                 : std_logic;<br \/>\n    end record;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Altera VHDL Examples Die Hardwarebeschreibungssprache VHDL OpenCores open source hardware IP-cores RegEx Look-around assertions Diese Konstrukte erweitern die regul\u00e4ren Ausdr\u00fccke um die M\u00f6glichkeit, kontextsensitive Bedingungen zu formulieren, ohne den Kontext selbst zu matchen. Das hei\u00dft, m\u00f6chte man alle Zeichenfolgen \u201eSport\u201c matchen, denen die Zeichenfolge \u201everein\u201c folgt, ohne dass jedoch die gematchte Zeichenfolge die Zeichenfolge \u201everein\u201c [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-1696","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/1696","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1696"}],"version-history":[{"count":10,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/1696\/revisions"}],"predecessor-version":[{"id":1808,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/1696\/revisions\/1808"}],"wp:attachment":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1696"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1696"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1696"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}