{"id":1679,"date":"2014-01-14T10:28:56","date_gmt":"2014-01-14T10:28:56","guid":{"rendered":"http:\/\/blog.bachi.net\/?p=1679"},"modified":"2014-01-14T12:16:07","modified_gmt":"2014-01-14T12:16:07","slug":"vhdl-types","status":"publish","type":"post","link":"https:\/\/blog.bachi.net\/?p=1679","title":{"rendered":"VHDL Types"},"content":{"rendered":"<h4>Standard<\/h4>\n<pre class=\"brush: plain; title: ; notranslate\" title=\"\">\r\nlibrary IEEE;\r\nuse IEEE.std_logic_1164.all;\r\nuse IEEE.std_logic_textio.all;\r\nuse IEEE.std_logic_arith.all;\r\nuse IEEE.numeric_bit.all;\r\nuse IEEE.numeric_std.all;\r\nuse IEEE.std_logic_signed.all;\r\nuse IEEE.std_logic_unsigned.all;\r\nuse IEEE.math_real.all;\r\nuse IEEE.math_complex.all;\r\n\r\nlibrary STD;\r\nuse STD.textio;\r\n<\/pre>\n<p><a href=\"http:\/\/www.csee.umbc.edu\/portal\/help\/VHDL\/stdpkg.html\">VHDL standard packages and types<\/a><\/p>\n<ul>\n<li>&#8216;X&#8217; usually is caused by two statements driving the same signal in opposite directions,i.e., &#8216;0&#8217; and &#8216;1&#8217;<\/li>\n<li>&#8216;Z&#8217; is used to build a tri stated output\/input<\/li>\n<li>&#8216;L&#8217; and &#8216;H&#8217; are used to model a pulldown or pullup respectively<\/li>\n<li>&#8216;-&#8216; is used in comparisons when you don&#8217;t care about certain bits in a vector<\/li>\n<\/ul>\n<p><a href=\"http:\/\/stackoverflow.com\/questions\/12504884\/std-logic-in-vhdl\">stackoverflow: std_logic in VHDL<\/a><\/p>\n<h4>Wikipedia<\/h4>\n<p><a href=\"http:\/\/de.wikipedia.org\/wiki\/Very_High_Speed_Integrated_Circuit_Hardware_Description_Language\">VHDL<\/a><br \/>\n<a href=\"http:\/\/en.wikipedia.org\/wiki\/Four_valued_logic\">Four-valued logic<\/a> (en)<br \/>\n<a href=\"http:\/\/en.wikipedia.org\/wiki\/IEEE_1164\">IEEE 1164<\/a> (en)<br \/>\n<a href=\"http:\/\/en.wikipedia.org\/wiki\/Dataflow_programming\">Dataflow programming<\/a> (en)<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Standard library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_textio.all; use IEEE.std_logic_arith.all; use IEEE.numeric_bit.all; use IEEE.numeric_std.all; use IEEE.std_logic_signed.all; use IEEE.std_logic_unsigned.all; use IEEE.math_real.all; use IEEE.math_complex.all; library STD; use STD.textio; VHDL standard packages and types &#8216;X&#8217; usually is caused by two statements driving the same signal in opposite directions,i.e., &#8216;0&#8217; and &#8216;1&#8217; &#8216;Z&#8217; is used to build a tri stated [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-1679","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/1679","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1679"}],"version-history":[{"count":9,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/1679\/revisions"}],"predecessor-version":[{"id":1688,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/1679\/revisions\/1688"}],"wp:attachment":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1679"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1679"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1679"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}