VHDL<\/h3>\n
VHDL Design Examples<\/a><\/p>\n This variable enables the resolving of ambiguous function overloading in favor of the “explicit” function declaration (not the one automatically created by the compiler for each type declaration). Using this variable makes QuestaSim compatible with common industry practice.<\/p>\n You can override this variable by specifying vcom -explicit.<\/p>\n Note that the library clause is not used to specify the working library into which the design unit is placed after compilation. The vcom command adds compiled design units to the current working library. By default, this is the library named work. To change the current working library, you can use vcom -work and specify the name of the desired target library.<\/p>\n For VHDL, the order of compilation is important. You must compile any entities or configurations before an architecture that references them.<\/p>\n In most vhdl programs you have already seen examples of packages and libraries. Here are two:<\/p>\n The packages are std_logic_1164<\/strong> and std_logic_signed<\/strong> and the library is ieee<\/strong>. Since the scope<\/strong> of the library statement extends over the entire file, it is not necessary to repeat that for the second package. It is thus tempting to come to the conclusion that the “library ieee;” statement indicates the “directory” in which the std_logic_1164 package is located. Note, however, where it is in Synplicity:<\/p>\n In the latter there is no mention of ieee<\/strong> at all. It is thus more appropriate to think of ieee<\/strong> as a pointer to the location of the package. The directory structure shown in those three examples depicts the directories where the packages are loaded when the software is installed. The pointer ieee<\/strong> is hardcoded in the compilers and thus there is no need for the user to associate that pointer with the directory structure, nor is it possible to put the packages anywhere else after the software has been loaded.<\/p>\n User libraries and packages are setup very similarly to the built-in ones. However, in that case, the user is responsible for the directory structure, the contents of the files, etc. Note that the user must then also set up the pointer to the package. The following shows a complete example of this arrangement. There are two ways to do this: 1) with the “work” directory; 2) with a user library.<\/p>\n Libraries and Packages in VHDL<\/a><\/p>\n WORK is not the name of a VHDL library. This may surprise some (or even most) VHDL designers, even experienced engineers. Most of the time, nobody gets bothered by this. But on occasion, it can cause great confusion and waste of time.<\/p>\n All knowledge about VHDL starts with the IEEE Standard VHDL Language Reference Manual. LRM for short. Not much is said about “WORK”, but in section 11.2 (in the LRM 1076-2000) you can read the following:<\/p>\n Let me repeat: WORK denotes the current working library.<\/p>\n This means that there is no library named WORK. Instead, the identifier WORK just refers to the current library. You can compare WORK with the Java concept of this. In Java this refers to this object, which obviously is different for each object. This makes me think of a silly joke of man who asks: “is this the second street to the right?”<\/p>\n Enough silliness. Much confusion comes from the fact that VHDL tools allow you to give the name “WORK” to a library:<\/p>\n That is as crazy as having a street address of John Doe, Ourstreet, MyHomeTown<\/em>. How will your mail ever get there? And that is exactly the problem with using WORK<\/strong> as a library name. Other libraries cannot refer to you. If another library (say alex) they would refer to work.yourpackage.all<\/span>, the VHDL analyser would read this as the alex.yourpackage.all<\/span>.<\/p>\n It would have been better if VHDL tools would refuse the explicit name of WORK<\/strong> for a library. It would have been better if WORK<\/strong> were a reserved keyword in VHDL. But hey, there is no way to change that now. The best you can do is be aware of this idiosyncrasy in VHDL and live with it. Preferably by avoiding WORK<\/strong> all together.<\/p>\n\n
\r\nVSIM 13> cd hdl\/simulation\/questa\r\nVSIM 13> pwd\r\nhdl\/simulation\/questa\r\nVSIM 13> do ..\/scripts\/do_all.do\r\n<\/pre>\n
\n
\n ![\"questasim_flow\"](\"http:\/\/blog.bachi.net\/wp-content\/uploads\/2014\/01\/questasim_flow-150x150.png\")
<\/a><\/td>\n<\/tr>\n<\/table>\nSummary: History of VHDL<\/h4>\n
\n
\n 1981<\/td>\n Initiated by US DoD to address hardware life-cycle crisis<\/td>\n<\/tr>\n \n 1983-85<\/td>\n Development of baseline language by Intermetrics, IBM and TI<\/td>\n<\/tr>\n \n 1986<\/td>\n All rights transferred to IEEE<\/td>\n<\/tr>\n \n 1987<\/td>\n Publication of IEEE Standard<\/td>\n<\/tr>\n \n 1987<\/td>\n Mil Std 454 requires comprehensive VHDL descriptions to be delivered with ASICs<\/td>\n<\/tr>\n \n 1994<\/td>\n Revised standard (named VHDL 1076-1993)<\/td>\n<\/tr>\n \n 2000<\/td>\n Revised standard (named VHDL 1076 2000, Edition)<\/td>\n<\/tr>\n \n 2002<\/td>\n Revised standard (named VHDL 1076-2002)<\/td>\n<\/tr>\n \n 2007<\/td>\n VHDL Procedural Language Application Interface standard (VHDL 1076c-2007)<\/td>\n<\/tr>\n \n 2009<\/td>\n Revised Standard (named VHDL 1076-2008)<\/td>\n<\/tr>\n<\/table>\n modelsim.ini Variables<\/h3>\n
Explicit<\/h4>\n
Specifying Resource Libraries<\/h4>\n
Compiling a VeriLog Design<\/h3>\n
\r\nVSIM 13> vlog [...]\r\n<\/pre>\n
Compiling a VHDL Design<\/h3>\n
\r\nVSIM 13> vcom -2002 -explicit -work ..\/questa\/work ..\/source\/top_tb.vhd\r\n-2002 Revision VHDL 1076-2002\r\n-explicit Enables the resolving of ambiguous function overloading\r\n-work <directory> Specify the name of the desired target library\r\n<source> VHDL source\r\n<\/pre>\n
Built-in Libraries and Packages<\/h4>\n
\r\nlibrary ieee;\r\nuse ieee.std_logic_1164.all;\r\nuse ieee.std_logic_signed.all;\r\n<\/pre>\n
\nIt’s instructive to show where the packages are physically located. For Altera Max+2 and Xilinx Foundation these locations typically are:<\/p>\n\r\nAltera: ~\\maxplus2\\vhdl93\\ieee\\std1164.vhd\r\nXilinx: ~\\fndtn\\synth\\lib\\packages\\ieee\\src\\std_logic_1164.vhd\r\n<\/pre>\n
\r\nSynplicty: ~\\synplcty\\LIB\\vhd\\std1164.vhd\r\n<\/pre>\n
User Libraries and Packages<\/h4>\n
WORK is not a VHDL Library<\/h4>\n
\r\nEvery design unit [...] is assumed to contain the following implicit context items [...]:\r\nlibrary STD, WORK; use STD.STANDARD.all;\r\n[...] Library logical name WORK denotes the current working library during a given analysis.\r\n<\/pre>\n
\r\nvlib work\r\nvcom -work work myfile.vhd\r\n<\/pre>\n