<\/p>\n
Test-and-set<\/a> Read\u2013modify\u2013write<\/a> <\/p>\n LDR\/STR – Load\/Store<\/a> LDREX – Load Register Exclusive<\/a><\/p>\n CPS – Change Processor State<\/a><\/p>\n <\/p>\n Which variable types\/sizes are atomic on STM32 microcontrollers?<\/a><\/p>\n And, per this link, the following is true for “basic data types implemented in ARM C and C++” (ie: on STM32):<\/p>\n <\/p>\n C\/C++ atomic operation on ARM9 and ARM Cortex-M4<\/a> For 8-bit\/16-bit\/32-bit data<\/strong>, provided that the memory instruction generated is a single <\/strong> One more thing to add: there is no 64-bit exclusive access instructions for Cortex-M4.<\/p>\n LDREX\/STREX on the M3,M4,M7<\/a><\/p>\n Each exclusive access sequence (typically contains a read-modify-write) of a semaphore variable is very short. So you can have as many mutex as you like, it is just not all of them being updated at the same time.<\/p>\n <\/p>\n STM32: LDREX\/STREX vs Interruptsperre<\/a><\/p>\n Wenn ich also LDREX ausf\u00fchre, wird der execlusive access monitor gesetzt. wenn nun ein Interrupt (Exception) kommt, wird er wieder gel\u00f6scht und STREX schl\u00e4gt fehl.<\/p>\n The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-Exclusive instruction. atomic-lib f\u00fcr stm32<\/a> Die korrekte Vorgehensweise ist:<\/p>\n __disable_irq intrinsic<\/a> Variante mit extra Klasse<\/p>\n Da ist ein __disable_interrupt()…. deterministischer. Was ist eure Erfahrung?<\/p>\n Sehr deterministisch und im Fall von DMA auch sehr sinnlos. Gegen DMA hilft die Abschaltung von Interrupts \u00fcberhaupt nicht. Bei mehreren Cores sieht es \u00e4hnlich aus.<\/p>\n Wenn man die Sorge hat, in diese Falle laufen zu k\u00f6nnen, dann kann man solche Spinlocks auch ent-determinisieren, indem das Verhalten (Timing) abh\u00e4ngig von einem Durchlaufz\u00e4hler variiert.<\/p>\n","protected":false},"excerpt":{"rendered":" Wikipedia Test-and-set Load-link\/store-conditional (LL\/SC) Load-link returns the current value of a memory location… …while a subsequent store-conditional to the same memory location will store a new value only if no updates have occurred to that location since the load-link. Together, this implements a lock-free atomic read-modify-write operation. Read\u2013modify\u2013write RMW-Befehl ARM Assembly LDR\/STR – Load\/Store LDM\/STM […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-11905","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/11905","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=11905"}],"version-history":[{"count":7,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/11905\/revisions"}],"predecessor-version":[{"id":12016,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=\/wp\/v2\/posts\/11905\/revisions\/12016"}],"wp:attachment":[{"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=11905"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=11905"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blog.bachi.net\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=11905"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
\nLoad-link\/store-conditional<\/a> (LL\/SC)<\/p>\n\n
\nRMW-Befehl<\/a><\/p>\n
\nARM Assembly<\/h3>\n
\nLDM\/STM – Load\/Store Multiple<\/a>
\nthe speed of arm assembly ldm and ldr<\/a><\/p>\nCortex-M0+<\/h4>\n
\r\nCPSID i ; Disable all interrupts except NMI (set PRIMASK)\r\nCPSIE i ; Enable interrupts (clear PRIMASK)\r\n<\/pre>\n
\nStackOverflow<\/h3>\n
\n
bool\/_Bool<\/code> is “byte-aligned” (1-byte-aligned)<\/li>\nint8_t\/uint8_t<\/code> is “byte-aligned” (1-byte-aligned)<\/li>\nint16_t\/uint16_t<\/code> is “halfword-aligned” (2-byte-aligned)<\/li>\nint32_t\/uint32_t<\/code> is “word-aligned” (4-byte-aligned)<\/li>\nint64_t\/uint64_t<\/code> is “doubleword-aligned” (8-byte-aligned) <-- NOT GUARANTEED ATOMIC<\/strong><\/li>\nfloat <\/code>is “word-aligned” (4-byte-aligned)<\/li>\ndouble <\/code>is “doubleword-aligned” (8-byte-aligned) <-- NOT GUARANTEED ATOMIC<\/strong><\/li>\nlong double<\/code> is “doubleword-aligned” (8-byte-aligned) <-- NOT GUARANTEED ATOMIC<\/strong><\/li>\n
\nARM Community<\/h3>\n
\nAccess of 64-bit data<\/strong> can be interrupted on Cortex-M3\/M4:<\/p>\n\n
LDM\/STM<\/code> instructions, as Jens said, the instruction can get interrupted in the middle, the processor execute the ISR and then resume the LDM\/STM<\/code> from where it was interrupted.<\/li>\nLDR\/STR<\/code> to access a 64-bit data.<\/li>\n<\/ul>\nLDR\/STR<\/code> instruction, interrupt cannot happen in between<\/strong>. The external memory controller might convert 16-bit \/ 32-bit access into multiple transfers on the memory bus, but the processor doesn’t know this and will wait until the transfer is done before taking the interrupt.<\/p>\n
\nmikrocontroller.net<\/h3>\n
\nThe processor removes its exclusive access tag if:<\/p>\n\n
\nInterrupts ein-\/ausschalten beim ARM cortex-M3<\/a><\/p>\n\r\nsomeNonAtomicCode();\r\nATOMIC_BLOCK(...)\r\n{\r\n doSomeThing();\r\n \/\/ some comment\r\n doAtomicStuff();\r\n \/\/ another comment\r\n lastAtomicOperation();\r\n}\r\nsomeNonAtomicCode();\r\n<\/pre>\n\r\ntemplate <typename F> inline void doAtomic (F f) {\r\n __disable_irq ();\r\n f ();\r\n __enable_irq ();\r\n}\r\nint main () {\r\n doAtomic ([] () {\r\n \/\/ ... gesch\u00fctzte Operationen ...\r\n });\r\n}\r\n<\/pre>\n\r\n for( __disable_irq(), uint8_t cont = 1; cont == 1; __enable_irq(), cont = 0 )\r\n {\r\n Anweisungen ....\r\n }\r\n\r\n#define ATOMIC_BLOCK() for( __disable_irq(), uint8_t __cont = 1; __cont == 1; __enable_irq(), __cont = 0 )\r\n<\/pre>\n\n
\ndisable interrupts and enable interrupts if they where enabled<\/a><\/p>\n\r\n__istate_t interruptstate = __get_interrupt_state();\r\n__disable_interrupt();\r\n\/\/ Atomarer Block\u2026\r\n__set_interrupt_state(interruptstate);\r\n<\/pre>\n
\r\nclass IRQLocker {\r\n private:\r\n uint32_t m;\r\n public:\r\n inline IRQLocker () { m = __get_PRIMASK (); __disable_irq (); }\r\n inline ~IRQLocker () { if (m == 0) __enable_irq (); }\r\n};\r\ntemplate <typename F>\r\ninline void doAtomic (F f) {\r\n IRQLocker l;\r\n f ();\r\n}\r\nvoid test1 () {\r\n doAtomic ([] () {\r\n \/* tu was atomisches *\/\r\n });\r\n}\r\nvoid test2 () {\r\n {\r\n IRQLocker l;\r\n \/* tu was atomisches *\/\r\n } \/\/ bei der Schlie\u00dfenden Klammer erfolgt das entsperren\r\n}\r\n<\/pre>\n\r\nbool ATOMIC_int32Add(int32_t *var, int32_t off)\r\n{\r\n int32_t tempVal;\r\n int32_t lockedOut;\r\n do\r\n {\r\n tempVal = (int32_t) __LDREX((unsigned long *)var); \r\n tempVal += off;\r\n lockedOut = __STREX(tempVal,(unsigned long *)var); \r\n }\r\n while ( lockedOut ); \/\/ lockedOut: 0==Success, 1==instruction is locked out\r\n __DMB(10); \/\/ recommended by arm -> make sure every memory access is done\r\n return true;\r\n}\r\n<\/pre>\n