October | 2015 | Andreas' Blog

grep -r sysenter .
grep -r sysexit .
grep -r db_inst_0f0x .
grep -r db_inst_0f .
grep -r "int 0x80" .
grep -r "syscall" .
grep -r "sys/syscall.h" .
grep -r "sy_call" .
grep -r sigtramp.S .
grep -r "NON_GPROF_ENTRY(sigcode)" .
grep -r "sigcode" .
grep -r SYS_sigreturn .

#include <sys/syscall.h>

./powerpc/booke/vm_machdep.c
./powerpc/booke/trap.c:

./i386/i386/trap.c
./i386/i386/elf_machdep.c
./i386/i386/locore.s
./i386/xen/locore.s

./arm/arm/sys_machdep.c
./arm/arm/vm_machdep.c
./arm/arm/trap.c
./arm/arm/locore.S
./arm/arm/elf_machdep.c

./amd64/amd64/trap.c
./amd64/amd64/elf_machdep.c
./amd64/ia32/ia32_signal.c
./amd64/ia32/ia32_sigtramp.S
./amd64/ia32/ia32_reg.c
./amd64/ia32/ia32_syscall.c

SYS_syscall 
 
cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)

/*
 * System call handler for native binaries.  The trap frame is already
 * set up by the assembler trampoline and a pointer to it is saved in
 * td_frame.
 */
void
amd64_syscall(struct thread *td, int traced)
{
    [...]
}

./kern/subr_syscall.c:syscallenter(struct thread *td, struct syscall_args *sa)

static inline int
syscallenter(struct thread *td, struct syscall_args *sa)
{
        struct proc *p;
        int error, traced;

        PCPU_INC(cnt.v_syscall);
        p = td->td_proc;
        
        error = (p->p_sysent->sv_fetch_syscall_args)(td, sa);


                error = syscall_thread_enter(td, sa->callp);

                AUDIT_SYSCALL_ENTER(sa->code, td);
                error = (sa->callp->sy_call)(td, sa->args);
                AUDIT_SYSCALL_EXIT(error, td);

                syscall_thread_exit(td, sa->callp);
}

./amd64/amd64/db_trace.c:       sy_call_t *f;
./amd64/amd64/db_trace.c:               f = p->p_sysent->sv_table[number].sy_call;

ARM

The arguments of sys_sigreturn
svn commit: r245414 – head/sys/arm/arm/locore.S

==================================================

i386

Wikipedia: INT (x86 instruction)

ARM

List of ARM microarchitectures

ARM9E (ARMv5TEJ => ARM926EJ-S)
ARM10E (ARMv5TEJ => ARM1026EJ-S)
ARM11 (ARMv6Z => ARM1176JZ(F)-S)
Cortex-M (ARMv7E-M => Cortex-M4)
Cortex-A 32-bit (ARMv7-A => Cortex-A17)
Cortex-A 64-bit (ARMv8-A => Cortex-A57)

Thumb software interrupt and breakpoint instructions > Software interrupt (SWI)
Developing software for Cortex-M3 > Supervisor Calls (SVC) => formerly SWI
ARM and Thumb Instructions > Hypervisor Call (HVC) (Virtualization Extensions)
SWI : SoftWare Interrupt
Keil: SWI Functions, run in Supervisor Mode of ARM7 and ARM9, interrupt protected
Keil: SVC Functions, run in Privileged Handler Mode of the Cortex-M core
Are ARM instructuons SWI and SVC exactly same thing?
How to use the SWI in ARM Cortex A9 for enabling the IRQ interrupt?
Which Cortex-M3 interrupts can I use for general purpose work?
Effective Use of ARM Cortex-M3 SVCall

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