| Header File |
Processor |
| core_cm0.h |
for the Cortex-M0 processor |
| core_cm0plus.h |
for the Cortex-M0+ processor |
| core_cm3.h |
for the Cortex-M3 processor |
| core_cm4.h |
for the Cortex-M4 processor |
| core_cm7.h |
for the Cortex-M7 processor |
| core_cm23.h |
for the Cortex-M23 processor |
| core_cm33.h |
for the Cortex-M33 processor |
| core_sc000.h |
for the SecurCore SC000 processor |
| core_sc300.h |
for the SecurCore SC300 processor |
| core_armv8mbl.h |
for the Armv8-M Baseline processor |
| core_armv8mml.h |
for the Armv8-M Mainline processor |
APSR_Type
IPSR_Type
xPSR_Type
CONTROL_Type
NVIC_Type
SCB_Type
SCnSCB_Type
SysTick_Type
ITM_Type
DWT_Type
TPI_Type
MPU_Type
FPU_Type
CoreDebug_Type
typedef enum {
/* === ARM Cortex-M4 Specific Interrupt Numbers ======================================== */
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on */
/* Power up and warm reset */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, */
/* cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, */
/* including Access Violation */
/* and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, */
/* Memory Access Fault, */
/* other address/memory */
/* related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. */
/* Undef Instruction, */
/* Illegal State Transition */
SVCall_IRQn = -5, /*!< -5 System Service Call via */
/* SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for SV */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* === nrf52 Specific Interrupt Numbers ================================================ */
POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
RADIO_IRQn = 1, /*!< 1 RADIO */
UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
NFCT_IRQn = 5, /*!< 5 NFCT */
GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
SAADC_IRQn = 7, /*!< 7 SAADC */
TIMER0_IRQn = 8, /*!< 8 TIMER0 */
TIMER1_IRQn = 9, /*!< 9 TIMER1 */
TIMER2_IRQn = 10, /*!< 10 TIMER2 */
RTC0_IRQn = 11, /*!< 11 RTC0 */
TEMP_IRQn = 12, /*!< 12 TEMP */
RNG_IRQn = 13, /*!< 13 RNG */
ECB_IRQn = 14, /*!< 14 ECB */
CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
WDT_IRQn = 16, /*!< 16 WDT */
RTC1_IRQn = 17, /*!< 17 RTC1 */
QDEC_IRQn = 18, /*!< 18 QDEC */
COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
TIMER3_IRQn = 26, /*!< 26 TIMER3 */
TIMER4_IRQn = 27, /*!< 27 TIMER4 */
PWM0_IRQn = 28, /*!< 28 PWM0 */
PDM_IRQn = 29, /*!< 29 PDM */
MWU_IRQn = 32, /*!< 32 MWU */
PWM1_IRQn = 33, /*!< 33 PWM1 */
PWM2_IRQn = 34, /*!< 34 PWM2 */
SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
RTC2_IRQn = 36, /*!< 36 RTC2 */
I2S_IRQn = 37, /*!< 37 I2S */
FPU_IRQn = 38 /*!< 38 FPU */
} IRQn_Type;
/* Memory mapping of Cortex-M4 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
typedef struct
{
__IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24U];
__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[24U];
__IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24U];
__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24U];
__IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
uint32_t NVIC_GetPriorityGrouping(void)
void NVIC_EnableIRQ(IRQn_Type IRQn)
void NVIC_DisableIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetActive(IRQn_Type IRQn)
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
void NVIC_SystemReset(void)
uint32_t SysTick_Config(uint32_t ticks)
uint32_t ITM_SendChar (uint32_t ch)
int32_t ITM_ReceiveChar (void)
int32_t ITM_CheckChar (void)
void __enable_irq(void)
void __disable_irq(void)
uint32_t __get_CONTROL(void)
void __set_CONTROL(uint32_t control)
uint32_t __get_IPSR(void)
uint32_t __get_APSR(void)
uint32_t __get_xPSR(void)
uint32_t __get_PSP(void)
void __set_PSP(uint32_t topOfProcStack)
uint32_t __get_MSP(void)
void __set_MSP(uint32_t topOfMainStack)
uint32_t __get_PRIMASK(void)
void __set_PRIMASK(uint32_t priMask)
void __enable_fault_irq(void)
void __disable_fault_irq(void)
uint32_t __get_BASEPRI(void)
void __set_BASEPRI(uint32_t value)
void __set_BASEPRI_MAX(uint32_t value)
uint32_t __get_FAULTMASK(void)
void __set_FAULTMASK(uint32_t faultMask)
uint32_t __get_FPSCR(void)
void __set_FPSCR(uint32_t fpscr)
void __NOP(void)
void __WFI(void)
void __WFE(void)
void __SEV(void)
void __ISB(void)
void __DSB(void)
void __DMB(void)
uint32_t __REV(uint32_t value)
uint32_t __REV16(uint32_t value)
int32_t __REVSH(int32_t value)
uint32_t __ROR(uint32_t op1, uint32_t op2)
uint32_t __RBIT(uint32_t value)
uint8_t __LDREXB(volatile uint8_t *addr)
uint16_t __LDREXH(volatile uint16_t *addr)
uint32_t __LDREXW(volatile uint32_t *addr)
uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
void __CLREX(void)
uint32_t __RRX(uint32_t value)
uint8_t __LDRBT(volatile uint8_t *addr)
uint16_t __LDRHT(volatile uint16_t *addr)
uint32_t __LDRT(volatile uint32_t *addr)
void __STRBT(uint8_t value, volatile uint8_t *addr)
void __STRHT(uint16_t value, volatile uint16_t *addr)
void __STRT(uint32_t value, volatile uint32_t *addr)
uint32_t __SADD8(uint32_t op1, uint32_t op2)
uint32_t __QADD8(uint32_t op1, uint32_t op2)
uint32_t __SHADD8(uint32_t op1, uint32_t op2)
uint32_t __UADD8(uint32_t op1, uint32_t op2)
uint32_t __UQADD8(uint32_t op1, uint32_t op2)
uint32_t __UHADD8(uint32_t op1, uint32_t op2)
uint32_t __SSUB8(uint32_t op1, uint32_t op2)
uint32_t __QSUB8(uint32_t op1, uint32_t op2)
uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
uint32_t __USUB8(uint32_t op1, uint32_t op2)
uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
uint32_t __SADD16(uint32_t op1, uint32_t op2)
uint32_t __QADD16(uint32_t op1, uint32_t op2)
uint32_t __SHADD16(uint32_t op1, uint32_t op2)
uint32_t __UADD16(uint32_t op1, uint32_t op2)
uint32_t __UQADD16(uint32_t op1, uint32_t op2)
uint32_t __UHADD16(uint32_t op1, uint32_t op2)
uint32_t __SSUB16(uint32_t op1, uint32_t op2)
uint32_t __QSUB16(uint32_t op1, uint32_t op2)
uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
uint32_t __USUB16(uint32_t op1, uint32_t op2)
uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
uint32_t __SASX(uint32_t op1, uint32_t op2)
uint32_t __QASX(uint32_t op1, uint32_t op2)
uint32_t __SHASX(uint32_t op1, uint32_t op2)
uint32_t __UASX(uint32_t op1, uint32_t op2)
uint32_t __UQASX(uint32_t op1, uint32_t op2)
uint32_t __UHASX(uint32_t op1, uint32_t op2)
uint32_t __SSAX(uint32_t op1, uint32_t op2)
uint32_t __QSAX(uint32_t op1, uint32_t op2)
uint32_t __SHSAX(uint32_t op1, uint32_t op2)
uint32_t __USAX(uint32_t op1, uint32_t op2)
uint32_t __UQSAX(uint32_t op1, uint32_t op2)
uint32_t __UHSAX(uint32_t op1, uint32_t op2)
uint32_t __USAD8(uint32_t op1, uint32_t op2)
uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
uint32_t __UXTB16(uint32_t op1)
uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
uint32_t __SXTB16(uint32_t op1)
uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
uint32_t __SMUAD (uint32_t op1, uint32_t op2)
uint32_t __SMUADX (uint32_t op1, uint32_t op2)
uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
uint32_t __SMUSD (uint32_t op1, uint32_t op2)
uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
uint32_t __SEL (uint32_t op1, uint32_t op2)
int32_t __QADD( int32_t op1, int32_t op2)
int32_t __QSUB( int32_t op1, int32_t op2)
uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)