Category Archives: Uncategorized

nRF5 SDK: SoftDevice

ARM Assembly

       sd_ble_enable(uint32_t * p_app_ram_base)

#define SVCALL(number, return_type, signature)          \
  static return_type signature                          \
  {                                                     \
    __asm(                                              \
        "svc %0\n"                                      \
        "bx r14" : : "I" (GCC_CAST_CPP number) : "r0"   \

ARM GCC Inline Assembler Kochbuch
ARM GCC Inline Assembler Cookbook
GCC Extended Asm – Assembler Instructions with C Expression Operands
ARM GCC Inline Assembler Cookbook (PDF)
Writing inline assembly code

Stack Trace


void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info)

nrf_sdm.h   uint32_t     sd_softdevice_enable(&clock_lf_cfg, app_error_fault_handler)
nrf_sdh.c   ret_code_t   nrf_sdh_enable_request(void)
main.c      void         ble_stack_init(void)
main.c      int          main(void)


Specifying Attributes of Variables – section
Analyzing the Linker Map file with a little help from the ELF and the DWARF, A windows application to view and analyze information from the linker generated Map file

static nrf_sdh_ble_evt_observer_t m_ble_observer
__attribute__ ((section(".sdh_ble_observers3")))
__attribute__((used)) = {
    .handler   = ble_evt_handler,
    .p_context = NULL


section_name = sdh_ble_observers3
section_var  = static nrf_sdh_ble_evt_observer_t m_ble_observer

#define NRF_SECTION_ITEM_REGISTER(section_name, section_var) \
    section_var __attribute__ ((section("." STRINGIFY(section_name)))) __attribute__((used))


#define NRF_SECTION_SET_ITEM_REGISTER(_name, _priority, _var)
    NRF_SECTION_ITEM_REGISTER(CONCAT_2(_name, _priority), _var)


                             _name    = m_ble_observer
                             _prio    = 3
                             _handler = ble_evt_handler,
                             _context = NULL
#define NRF_SDH_BLE_OBSERVER(_name, _prio, _handler, _context)
    static nrf_sdh_ble_evt_observer_t _name
) =
    .handler   = _handler,
    .p_context = _context


#define APP_BLE_OBSERVER_PRIO           3

// Register a handler for BLE events.
NRF_SDH_BLE_OBSERVER(m_ble_observer, APP_BLE_OBSERVER_PRIO, ble_evt_handler, NULL);


/\*\*<[a-zA-Z .\\@_]*\*/
[,]?[ ]*/\*\*<[a-zA-Z ();,.\\@_]*\*/

ble_advertising_t    p_advertising->adv_handle
ble_advertising_t    p_advertising->evt_handler
ble_advertising_t    p_advertising->error_handler

uint32_t sd_ble_gap_adv_set_configure(...)
uint32_t ble_advertising_init(...)
void     advertising_init() -> init.evt_handler = on_adv_evt
int      main(void)

static void on_adv_evt(ble_adv_evt_t ble_adv_evt)
static void ble_evt_handler(ble_evt_t const * p_ble_evt, void * p_context)

typedef enum {
} ble_adv_evt_t;




uint32_t sd_ble_enable(uint32_t * p_app_ram_base)
uint32_t sd_ble_cfg_set(uint32_t cfg_id, ble_cfg_t const * p_cfg, uint32_t app_ram_base)
uint32_t sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len)
uint32_t sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type)
uint32_t sd_ble_uuid_vs_remove(uint8_t *p_uuid_type)
uint32_t sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid)
uint32_t sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le)
uint32_t sd_ble_version_get(ble_version_t *p_version)
uint32_t sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block)
uint32_t sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt)
uint32_t sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)
uint32_t sd_ble_gap_addr_set(ble_gap_addr_t const *p_addr)
uint32_t sd_ble_gap_addr_get(ble_gap_addr_t *p_addr)
uint32_t sd_ble_gap_adv_addr_get(uint8_t adv_handle, ble_gap_addr_t *p_addr)
uint32_t sd_ble_gap_whitelist_set(ble_gap_addr_t const * const * pp_wl_addrs, uint8_t len)
uint32_t sd_ble_gap_device_identities_set(ble_gap_id_key_t const * const * pp_id_keys, ble_gap_irk_t const * const * pp_local_irks, uint8_t len)
uint32_t sd_ble_gap_privacy_set(ble_gap_privacy_params_t const *p_privacy_params)
uint32_t sd_ble_gap_privacy_get(ble_gap_privacy_params_t *p_privacy_params)
uint32_t sd_ble_gap_adv_set_configure(uint8_t *p_adv_handle, ble_gap_adv_data_t const *p_adv_data, ble_gap_adv_params_t const *p_adv_params)
uint32_t sd_ble_gap_adv_start(uint8_t adv_handle, uint8_t conn_cfg_tag)
uint32_t sd_ble_gap_adv_stop(uint8_t adv_handle)
uint32_t sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params)
uint32_t sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code)
uint32_t sd_ble_gap_tx_power_set(uint8_t role, uint16_t handle, int8_t tx_power)
uint32_t sd_ble_gap_appearance_set(uint16_t appearance)
uint32_t sd_ble_gap_appearance_get(uint16_t *p_appearance)
uint32_t sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params)
uint32_t sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params)
uint32_t sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len)
uint32_t sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len)
uint32_t sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)
uint32_t sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset)
uint32_t sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key)
uint32_t sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey)
uint32_t sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not)
uint32_t sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own)
uint32_t sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer)
uint32_t sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info)
uint32_t sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info)
uint32_t sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec)
uint32_t sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count)
uint32_t sd_ble_gap_rssi_stop(uint16_t conn_handle)
uint32_t sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi, uint8_t *p_ch_index)
uint32_t sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params, ble_data_t const * p_adv_report_buffer)
uint32_t sd_ble_gap_scan_stop(void)
uint32_t sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params, uint8_t conn_cfg_tag)
uint32_t sd_ble_gap_connect_cancel(void)
uint32_t sd_ble_gap_phy_update(uint16_t conn_handle, ble_gap_phys_t const *p_gap_phys)
uint32_t sd_ble_gap_data_length_update(uint16_t conn_handle, ble_gap_data_length_params_t const *p_dl_params, ble_gap_data_length_limitation_t *p_dl_limitation)
uint32_t sd_ble_gap_qos_channel_survey_start(uint32_t interval_us)
uint32_t sd_ble_gap_qos_channel_survey_stop(void)
uint32_t sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid)
uint32_t sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)
uint32_t sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)
uint32_t sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)
uint32_t sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range)
uint32_t sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset)
uint32_t sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count)
uint32_t sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params)
uint32_t sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle)
uint32_t sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range)
uint32_t sd_ble_gattc_exchange_mtu_request(uint16_t conn_handle, uint16_t client_rx_mtu)
uint32_t sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle)
uint32_t sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle)
uint32_t sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles)
uint32_t sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle)
uint32_t sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)
uint32_t sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)
uint32_t sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params)
uint32_t sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle)
uint32_t sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params)
uint32_t sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags)
uint32_t sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags)
uint32_t sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle)
uint32_t sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md)
uint32_t sd_ble_gatts_exchange_mtu_reply(uint16_t conn_handle, uint16_t server_rx_mtu)
uint32_t sd_ble_l2cap_ch_setup(uint16_t conn_handle, uint16_t *p_local_cid, ble_l2cap_ch_setup_params_t const *p_params)
uint32_t sd_ble_l2cap_ch_release(uint16_t conn_handle, uint16_t local_cid)
uint32_t sd_ble_l2cap_ch_rx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)
uint32_t sd_ble_l2cap_ch_tx(uint16_t conn_handle, uint16_t local_cid, ble_data_t const *p_sdu_buf)
uint32_t sd_ble_l2cap_ch_flow_control(uint16_t conn_handle, uint16_t local_cid, uint16_t credits, uint16_t *p_credits)
uint32_t sd_mbr_command(sd_mbr_command_t* param)
uint32_t sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler)
uint32_t sd_softdevice_disable(void)
uint32_t sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled)
uint32_t sd_softdevice_vector_table_base_set(uint32_t address)
uint32_t sd_mutex_new(nrf_mutex_t * p_mutex)
uint32_t sd_mutex_acquire(nrf_mutex_t * p_mutex)
uint32_t sd_mutex_release(nrf_mutex_t * p_mutex)
uint32_t sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity)
uint32_t sd_rand_application_bytes_available_get(uint8_t * p_bytes_available)
uint32_t sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length)
uint32_t sd_power_reset_reason_get(uint32_t * p_reset_reason)
uint32_t sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk)
uint32_t sd_power_mode_set(uint8_t power_mode)
uint32_t sd_power_system_off(void)
uint32_t sd_power_pof_enable(uint8_t pof_enable)
uint32_t sd_power_pof_threshold_set(uint8_t threshold)
uint32_t sd_power_ram_power_set(uint8_t index, uint32_t ram_powerset)
uint32_t sd_power_ram_power_clr(uint8_t index, uint32_t ram_powerclr)
uint32_t sd_power_ram_power_get(uint8_t index, uint32_t * p_ram_power)
uint32_t sd_power_gpregret_set(uint32_t gpregret_id, uint32_t gpregret_msk)
uint32_t sd_power_gpregret_clr(uint32_t gpregret_id, uint32_t gpregret_msk)
uint32_t sd_power_gpregret_get(uint32_t gpregret_id, uint32_t *p_gpregret)
uint32_t sd_power_dcdc_mode_set(uint8_t dcdc_mode)
uint32_t sd_clock_hfclk_request(void)
uint32_t sd_clock_hfclk_release(void)
uint32_t sd_clock_hfclk_is_running(uint32_t * p_is_running)
uint32_t sd_app_evt_wait(void)
uint32_t sd_ppi_channel_enable_get(uint32_t * p_channel_enable)
uint32_t sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk)
uint32_t sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk)
uint32_t sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)
uint32_t sd_ppi_group_task_enable(uint8_t group_num)
uint32_t sd_ppi_group_task_disable(uint8_t group_num)
uint32_t sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk)
uint32_t sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk)
uint32_t sd_radio_notification_cfg_set(uint8_t type, uint8_t distance)
uint32_t sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data)
uint32_t sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks)
uint32_t sd_evt_get(uint32_t * p_evt_id)
uint32_t sd_temp_get(int32_t * p_temp)
uint32_t sd_flash_write(uint32_t * p_dst, uint32_t const * p_src, uint32_t size)
uint32_t sd_flash_page_erase(uint32_t page_number)
uint32_t sd_flash_protect(uint32_t block_cfg0, uint32_t block_cfg1, uint32_t block_cfg2, uint32_t block_cfg3)
uint32_t sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)
uint32_t sd_radio_session_close(void)
uint32_t sd_radio_request(nrf_radio_request_t const * p_request)
uint32_t sd_protected_register_write(volatile uint32_t * p_register, uint32_t value)

3D Druck/Print: STL to STEP

Convert STL to STEP

 1. New
 2. Import -> STL
3a. Workbench "Mesh Design" 
3b. Meshes menu > Analyze > Evaluate & Repair mesh
3c. Select mesh from "Evaluate & Repair" pane
3d. Go down the list, click "Analyze" and then "Repair"
    If any option makes your mesh look terrible, skip it.
4a. Workbench "Part" 
4b. Part menu > Convert to shape
4c. Part menu > Convert to solid
5. Export as STEP File "STEP with colors (*.step *.stp)"

PDF2SVG: Convert PDF to SVG

$ pdf2svg
$ pdftocairo -svg
$ inkscape -l out.svg in.pdf
$ inkscape \
  --without-gui \
  --file=input.pdf \
$ pstoedit -f plot-svg -dt -ssp eqn.svg

Fonts don’t match

An option seems to be to first convert the fonts to path on the pdf side with:

$ gs -o target.pdf -dNoOutputFonts -sDEVICE=pdfwrite source.pdf


Convert PDF to SVG by command line
convert pdf to svg
PDF to SVG conversion with grouping and proper text conversion
Convert PDF to clean SVG?

nRF5 SDK: Windows 10 and BLE


nRFUart Example – “Exception in StartMasterEmulator: -100”
s there a PC (win / debian) application or source for NUS?
Integrated bluetooth device on windows and NUS service
BLE interface in visual basic
PC(Central) and NRF51822 (Peripheral) communication
Trouble with nRF UART in Windows

Bluetooth Client (Linux / Windows)

nRF Connect for Desktop
Qt Bluetooth
Bluetooth Low Energy Overview
Microsoft Store: Bluetooth LE Explorer

Bluetooth LE Lab, Desktop library for BLE development using nRF5, nrfutil python library and command line client


nRF5284 Dongle
The nRF52840 USB Dongle Tutorial (Part 1)

Terminal (TTY), Pseudo-Terminal (PTY), Shell

Terminal A terminal was that what seemed like 30 kg piece of solid cast iron frame wrapped in cream-colour plastic case with a glass display and keyboard in front of you
Terminal Emulation
Shell A shell was a program running on the main computer interpreting your commands.
terminal, tty text input/output environment
terminal emulator, pseudo-tty
console physical terminal
shell command line interpreter
pty “pseudo terminal”
pts “pseudo terminal slave”: login device when connecting through the network or a console (e.g. ssh).
tty “teletype”: serial or console connections (text mode)

Must Read Tutorial

The TTY demystified
What Is Tty/pty/pts

Change Content on Terminal

Overwrite last line on terminal
How to change the contents of a line on the terminal as opposed to writing a new one?
How do I keep terminal line from overwriting itself?


“The curses library (ncurses) provides a terminal-independent method of controlling character screens.”
Curses programming
urwid, Console user interface library for Python

Terminal Codes

Terminal codes (ANSI/VT100) introduction

What is a Terminal/Console/Shell (StackOverFlow / StackExchange)

What is the difference between **pts** and **tty** and **:0**?
Terminal vs bash? [duplicate]
What are pseudo terminals (pty/tty)?
What do pty and tty mean?
How to get the tty in which bash is running?
What is the exact difference between a ‘terminal’, a ‘shell’, a ‘tty’ and a ‘console’?



curses (programming library)
Text-based user interface


Zeichenorientierte Benutzerschnittstelle


terminfo, terminal capability data base
getty, set terminal mode
agetty, alternative Linux getty


  • nRF52 is only a TAG
  • nRF52 cannot read other TAGs
  • A reader is required for that: NXP RC522, NXP PN532, AS3909/AS3910
Type 1 Tag

Broadcom Topaz

Type 2 Tag

NXP Mifare Ultralight, NXP Mifare Ultralight C, NXP NTAG

Type 3 Tag

Sony FeliCa

Type 4 Tag


RFID Selection Guide (PDF)
RFID vs. NFC: What’s the Difference?
NFC Chiptypen
nRF52 as NFC reader


nRF52 NFC operation modes
nRF52 -PN532 – reading Mifare Classic
nRF52 write NFC Tag

nRF5 SDK: Peripheral Interface

AAR Accelerated address resolver
ACL Access control lists
CCM AES CCM mode encryption
COMP Comparator
CRYPTOCELL ARM TrustZone CryptoCell 310
ECB AES electronic codebook mode encryption
EGU Event generator unit
GPIO General purpose input/output
GPIOTE GPIO tasks and events
I2S Inter-IC sound interface
LPCOMP Low power comparator
MWU Memory watch unit
NFCT Near field communication tag
PDM Pulse density modulation interface
PPI Programmable peripheral interconnect
PWM Pulse width modulation
QDEC Quadrature decoder
QSPI Quad serial peripheral interface
RADIO 2.4 GHz radio
RNG Random number generator
RTC Real-time counter
SAADC Successive approximation analog-to-digital converter
SPI Serial peripheral interface master
SPIM Serial peripheral interface master with EasyDMA
SPIS Serial peripheral interface slave with EasyDMA
SWI Software interrupts
TEMP Temperature sensor
TWI I2C compatible two-wire interface
TIMER Timer/counter
TWIM I2C compatible two-wire interface master with EasyDMA
TWIS I2C compatible two-wire interface slave with EasyDMA
UART Universal asynchronous receiver/transmitter
UARTE Universal asynchronous receiver/transmitter with EasyDMA
USBD Universal serial bus device
WDT Watchdog timer
Part of HAL (lowest layer!)
#define NRF_FICR      ((NRF_FICR_Type*)      NRF_FICR_BASE)
#define NRF_UICR      ((NRF_UICR_Type*)      NRF_UICR_BASE)
#define NRF_BPROT     ((NRF_BPROT_Type*)     NRF_BPROT_BASE)
#define NRF_POWER     ((NRF_POWER_Type*)     NRF_POWER_BASE)
#define NRF_CLOCK     ((NRF_CLOCK_Type*)     NRF_CLOCK_BASE)
#define NRF_RADIO     ((NRF_RADIO_Type*)     NRF_RADIO_BASE)
#define NRF_UARTE0    ((NRF_UARTE_Type*)     NRF_UARTE0_BASE)
#define NRF_UART0     ((NRF_UART_Type*)      NRF_UART0_BASE)
#define NRF_SPIM0     ((NRF_SPIM_Type*)      NRF_SPIM0_BASE)
#define NRF_SPIS0     ((NRF_SPIS_Type*)      NRF_SPIS0_BASE)
#define NRF_TWIM0     ((NRF_TWIM_Type*)      NRF_TWIM0_BASE)
#define NRF_TWIS0     ((NRF_TWIS_Type*)      NRF_TWIS0_BASE)
#define NRF_SPI0      ((NRF_SPI_Type*)       NRF_SPI0_BASE)
#define NRF_TWI0      ((NRF_TWI_Type*)       NRF_TWI0_BASE)
#define NRF_SPIM1     ((NRF_SPIM_Type*)      NRF_SPIM1_BASE)
#define NRF_SPIS1     ((NRF_SPIS_Type*)      NRF_SPIS1_BASE)
#define NRF_TWIM1     ((NRF_TWIM_Type*)      NRF_TWIM1_BASE)
#define NRF_TWIS1     ((NRF_TWIS_Type*)      NRF_TWIS1_BASE)
#define NRF_SPI1      ((NRF_SPI_Type*)       NRF_SPI1_BASE)
#define NRF_TWI1      ((NRF_TWI_Type*)       NRF_TWI1_BASE)
#define NRF_NFCT      ((NRF_NFCT_Type*)      NRF_NFCT_BASE)
#define NRF_SAADC     ((NRF_SAADC_Type*)     NRF_SAADC_BASE)
#define NRF_TIMER0    ((NRF_TIMER_Type*)     NRF_TIMER0_BASE)
#define NRF_TIMER1    ((NRF_TIMER_Type*)     NRF_TIMER1_BASE)
#define NRF_TIMER2    ((NRF_TIMER_Type*)     NRF_TIMER2_BASE)
#define NRF_RTC0      ((NRF_RTC_Type*)       NRF_RTC0_BASE)
#define NRF_TEMP      ((NRF_TEMP_Type*)      NRF_TEMP_BASE)
#define NRF_RNG       ((NRF_RNG_Type*)       NRF_RNG_BASE)
#define NRF_ECB       ((NRF_ECB_Type*)       NRF_ECB_BASE)
#define NRF_CCM       ((NRF_CCM_Type*)       NRF_CCM_BASE)
#define NRF_AAR       ((NRF_AAR_Type*)       NRF_AAR_BASE)
#define NRF_WDT       ((NRF_WDT_Type*)       NRF_WDT_BASE)
#define NRF_RTC1      ((NRF_RTC_Type*)       NRF_RTC1_BASE)
#define NRF_QDEC      ((NRF_QDEC_Type*)      NRF_QDEC_BASE)
#define NRF_COMP      ((NRF_COMP_Type*)      NRF_COMP_BASE)
#define NRF_SWI0      ((NRF_SWI_Type*)       NRF_SWI0_BASE)
#define NRF_EGU0      ((NRF_EGU_Type*)       NRF_EGU0_BASE)
#define NRF_SWI1      ((NRF_SWI_Type*)       NRF_SWI1_BASE)
#define NRF_EGU1      ((NRF_EGU_Type*)       NRF_EGU1_BASE)
#define NRF_SWI2      ((NRF_SWI_Type*)       NRF_SWI2_BASE)
#define NRF_EGU2      ((NRF_EGU_Type*)       NRF_EGU2_BASE)
#define NRF_SWI3      ((NRF_SWI_Type*)       NRF_SWI3_BASE)
#define NRF_EGU3      ((NRF_EGU_Type*)       NRF_EGU3_BASE)
#define NRF_SWI4      ((NRF_SWI_Type*)       NRF_SWI4_BASE)
#define NRF_EGU4      ((NRF_EGU_Type*)       NRF_EGU4_BASE)
#define NRF_SWI5      ((NRF_SWI_Type*)       NRF_SWI5_BASE)
#define NRF_EGU5      ((NRF_EGU_Type*)       NRF_EGU5_BASE)
#define NRF_TIMER3    ((NRF_TIMER_Type*)     NRF_TIMER3_BASE)
#define NRF_TIMER4    ((NRF_TIMER_Type*)     NRF_TIMER4_BASE)
#define NRF_PWM0      ((NRF_PWM_Type*)       NRF_PWM0_BASE)
#define NRF_PDM       ((NRF_PDM_Type*)       NRF_PDM_BASE)
#define NRF_NVMC      ((NRF_NVMC_Type*)      NRF_NVMC_BASE)
#define NRF_PPI       ((NRF_PPI_Type*)       NRF_PPI_BASE)
#define NRF_MWU       ((NRF_MWU_Type*)       NRF_MWU_BASE)
#define NRF_PWM1      ((NRF_PWM_Type*)       NRF_PWM1_BASE)
#define NRF_PWM2      ((NRF_PWM_Type*)       NRF_PWM2_BASE)
#define NRF_SPIM2     ((NRF_SPIM_Type*)      NRF_SPIM2_BASE)
#define NRF_SPIS2     ((NRF_SPIS_Type*)      NRF_SPIS2_BASE)
#define NRF_SPI2      ((NRF_SPI_Type*)       NRF_SPI2_BASE)
#define NRF_RTC2      ((NRF_RTC_Type*)       NRF_RTC2_BASE)
#define NRF_I2S       ((NRF_I2S_Type*)       NRF_I2S_BASE)
#define NRF_FPU       ((NRF_FPU_Type*)       NRF_FPU_BASE)
#define NRF_P0        ((NRF_GPIO_Type*)      NRF_P0_BASE)


Header File Processor
core_cm0.h for the Cortex-M0 processor
core_cm0plus.h for the Cortex-M0+ processor
core_cm3.h for the Cortex-M3 processor
core_cm4.h for the Cortex-M4 processor
core_cm7.h for the Cortex-M7 processor
core_cm23.h for the Cortex-M23 processor
core_cm33.h for the Cortex-M33 processor
core_sc000.h for the SecurCore SC000 processor
core_sc300.h for the SecurCore SC300 processor
core_armv8mbl.h for the Armv8-M Baseline processor
core_armv8mml.h for the Armv8-M Mainline processor
typedef enum {
/* ===  ARM Cortex-M4 Specific Interrupt Numbers  ======================================== */
  Reset_IRQn                = -15,              /*!< -15 Reset Vector, invoked on          */
                                                /*       Power up and warm reset           */
  NonMaskableInt_IRQn       = -14,              /*!< -14 Non maskable Interrupt,           */
                                                /*       cannot be stopped or preempted    */
  HardFault_IRQn            = -13,              /*!< -13 Hard Fault, all classes of Fault  */
  MemoryManagement_IRQn     = -12,              /*!< -12 Memory Management, MPU mismatch,  */
                                                /*       including Access Violation        */
                                                /*       and No Match                      */
  BusFault_IRQn             = -11,              /*!< -11 Bus Fault, Pre-Fetch-,            */
                                                /*       Memory Access Fault,              */
                                                /*       other address/memory              */
                                                /*       related Fault                     */
  UsageFault_IRQn           = -10,              /*!< -10 Usage Fault, i.e.                 */
                                                /*       Undef Instruction,                */
                                                /*       Illegal State Transition          */
  SVCall_IRQn               =  -5,              /*!<  -5 System Service Call via           */
                                                /*      SVC instruction                    */
  DebugMonitor_IRQn         =  -4,              /*!<  -4 Debug Monitor                     */
  PendSV_IRQn               =  -2,              /*!<  -2 Pendable request for SV           */
  SysTick_IRQn              =  -1,              /*!<  -1 System Tick Timer                 */
/* ===  nrf52 Specific Interrupt Numbers  ================================================ */
  POWER_CLOCK_IRQn          =   0,              /*!<  0 POWER_CLOCK                        */
  RADIO_IRQn                =   1,              /*!<  1 RADIO                              */
  UARTE0_UART0_IRQn         =   2,              /*!<  2 UARTE0_UART0                       */
  NFCT_IRQn                 =   5,              /*!<  5 NFCT                               */
  GPIOTE_IRQn               =   6,              /*!<  6 GPIOTE                             */
  SAADC_IRQn                =   7,              /*!<  7 SAADC                              */
  TIMER0_IRQn               =   8,              /*!<  8 TIMER0                             */
  TIMER1_IRQn               =   9,              /*!<  9 TIMER1                             */
  TIMER2_IRQn               =  10,              /*!< 10 TIMER2                             */
  RTC0_IRQn                 =  11,              /*!< 11 RTC0                               */
  TEMP_IRQn                 =  12,              /*!< 12 TEMP                               */
  RNG_IRQn                  =  13,              /*!< 13 RNG                                */
  ECB_IRQn                  =  14,              /*!< 14 ECB                                */
  CCM_AAR_IRQn              =  15,              /*!< 15 CCM_AAR                            */
  WDT_IRQn                  =  16,              /*!< 16 WDT                                */
  RTC1_IRQn                 =  17,              /*!< 17 RTC1                               */
  QDEC_IRQn                 =  18,              /*!< 18 QDEC                               */
  COMP_LPCOMP_IRQn          =  19,              /*!< 19 COMP_LPCOMP                        */
  SWI0_EGU0_IRQn            =  20,              /*!< 20 SWI0_EGU0                          */
  SWI1_EGU1_IRQn            =  21,              /*!< 21 SWI1_EGU1                          */
  SWI2_EGU2_IRQn            =  22,              /*!< 22 SWI2_EGU2                          */
  SWI3_EGU3_IRQn            =  23,              /*!< 23 SWI3_EGU3                          */
  SWI4_EGU4_IRQn            =  24,              /*!< 24 SWI4_EGU4                          */
  SWI5_EGU5_IRQn            =  25,              /*!< 25 SWI5_EGU5                          */
  TIMER3_IRQn               =  26,              /*!< 26 TIMER3                             */
  TIMER4_IRQn               =  27,              /*!< 27 TIMER4                             */
  PWM0_IRQn                 =  28,              /*!< 28 PWM0                               */
  PDM_IRQn                  =  29,              /*!< 29 PDM                                */
  MWU_IRQn                  =  32,              /*!< 32 MWU                                */
  PWM1_IRQn                 =  33,              /*!< 33 PWM1                               */
  PWM2_IRQn                 =  34,              /*!< 34 PWM2                               */
  SPIM2_SPIS2_SPI2_IRQn     =  35,              /*!< 35 SPIM2_SPIS2_SPI2                   */
  RTC2_IRQn                 =  36,              /*!< 36 RTC2                               */
  I2S_IRQn                  =  37,              /*!< 37 I2S                                */
  FPU_IRQn                  =  38               /*!< 38 FPU                                */
} IRQn_Type;
/* Memory mapping of Cortex-M4 Hardware */
#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */

#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */

typedef struct
  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
        uint32_t RESERVED0[24U];
  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
        uint32_t RSERVED1[24U];
  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
        uint32_t RESERVED2[24U];
  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
        uint32_t RESERVED3[24U];
  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
        uint32_t RESERVED4[56U];
  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
        uint32_t RESERVED5[644U];
  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
}  NVIC_Type;

typedef struct
  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
} SysTick_Type;

void     NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
uint32_t NVIC_GetPriorityGrouping(void)
void     NVIC_EnableIRQ(IRQn_Type IRQn)
void     NVIC_DisableIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
void     NVIC_SetPendingIRQ(IRQn_Type IRQn)
void     NVIC_ClearPendingIRQ(IRQn_Type IRQn)
uint32_t NVIC_GetActive(IRQn_Type IRQn)
void     NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
void     NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
void     NVIC_SystemReset(void)

uint32_t SysTick_Config(uint32_t ticks)

uint32_t ITM_SendChar (uint32_t ch)
int32_t  ITM_ReceiveChar (void)
int32_t  ITM_CheckChar (void)
void     __enable_irq(void)
void     __disable_irq(void)
uint32_t __get_CONTROL(void)
void     __set_CONTROL(uint32_t control)
uint32_t __get_IPSR(void)
uint32_t __get_APSR(void)
uint32_t __get_xPSR(void)
uint32_t __get_PSP(void)
void     __set_PSP(uint32_t topOfProcStack)
uint32_t __get_MSP(void)
void     __set_MSP(uint32_t topOfMainStack)
uint32_t __get_PRIMASK(void)
void     __set_PRIMASK(uint32_t priMask)
void     __enable_fault_irq(void)
void     __disable_fault_irq(void)
uint32_t __get_BASEPRI(void)
void     __set_BASEPRI(uint32_t value)
void     __set_BASEPRI_MAX(uint32_t value)
uint32_t __get_FAULTMASK(void)
void     __set_FAULTMASK(uint32_t faultMask)
uint32_t __get_FPSCR(void)
void     __set_FPSCR(uint32_t fpscr)

void     __NOP(void)
void     __WFI(void)
void     __WFE(void)
void     __SEV(void)
void     __ISB(void)
void     __DSB(void)
void     __DMB(void)
uint32_t __REV(uint32_t value)
uint32_t __REV16(uint32_t value)
 int32_t __REVSH(int32_t value)
uint32_t __ROR(uint32_t op1, uint32_t op2)
uint32_t __RBIT(uint32_t value)
uint8_t  __LDREXB(volatile uint8_t *addr)
uint16_t __LDREXH(volatile uint16_t *addr)
uint32_t __LDREXW(volatile uint32_t *addr)
uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
void     __CLREX(void)
uint32_t __RRX(uint32_t value)
uint8_t  __LDRBT(volatile uint8_t *addr)
uint16_t __LDRHT(volatile uint16_t *addr)
uint32_t __LDRT(volatile uint32_t *addr)
void     __STRBT(uint8_t value, volatile uint8_t *addr)
void     __STRHT(uint16_t value, volatile uint16_t *addr)
void     __STRT(uint32_t value, volatile uint32_t *addr)

uint32_t __SADD8(uint32_t op1, uint32_t op2)
uint32_t __QADD8(uint32_t op1, uint32_t op2)
uint32_t __SHADD8(uint32_t op1, uint32_t op2)
uint32_t __UADD8(uint32_t op1, uint32_t op2)
uint32_t __UQADD8(uint32_t op1, uint32_t op2)
uint32_t __UHADD8(uint32_t op1, uint32_t op2)
uint32_t __SSUB8(uint32_t op1, uint32_t op2)
uint32_t __QSUB8(uint32_t op1, uint32_t op2)
uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
uint32_t __USUB8(uint32_t op1, uint32_t op2)
uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
uint32_t __SADD16(uint32_t op1, uint32_t op2)
uint32_t __QADD16(uint32_t op1, uint32_t op2)
uint32_t __SHADD16(uint32_t op1, uint32_t op2)
uint32_t __UADD16(uint32_t op1, uint32_t op2)
uint32_t __UQADD16(uint32_t op1, uint32_t op2)
uint32_t __UHADD16(uint32_t op1, uint32_t op2)
uint32_t __SSUB16(uint32_t op1, uint32_t op2)
uint32_t __QSUB16(uint32_t op1, uint32_t op2)
uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
uint32_t __USUB16(uint32_t op1, uint32_t op2)
uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
uint32_t __SASX(uint32_t op1, uint32_t op2)
uint32_t __QASX(uint32_t op1, uint32_t op2)
uint32_t __SHASX(uint32_t op1, uint32_t op2)
uint32_t __UASX(uint32_t op1, uint32_t op2)
uint32_t __UQASX(uint32_t op1, uint32_t op2)
uint32_t __UHASX(uint32_t op1, uint32_t op2)
uint32_t __SSAX(uint32_t op1, uint32_t op2)
uint32_t __QSAX(uint32_t op1, uint32_t op2)
uint32_t __SHSAX(uint32_t op1, uint32_t op2)
uint32_t __USAX(uint32_t op1, uint32_t op2)
uint32_t __UQSAX(uint32_t op1, uint32_t op2)
uint32_t __UHSAX(uint32_t op1, uint32_t op2)
uint32_t __USAD8(uint32_t op1, uint32_t op2)
uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
uint32_t __UXTB16(uint32_t op1)
uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
uint32_t __SXTB16(uint32_t op1)
uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
uint32_t __SMUADX (uint32_t op1, uint32_t op2)
uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
uint32_t __SEL  (uint32_t op1, uint32_t op2)
 int32_t __QADD( int32_t op1,  int32_t op2)
 int32_t __QSUB( int32_t op1,  int32_t op2)
uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)